diff mbox series

[1/4] clk: debug: add support for setting clk_rate from debugfs

Message ID 20191001090202.26346-2-t-kristo@ti.com (mailing list archive)
State Changes Requested, archived
Headers show
Series clk: debugfs: add some simple debug functionality | expand

Commit Message

Tero Kristo Oct. 1, 2019, 9:01 a.m. UTC 
Debugfs entries for clock drivers don't allow writing to the nodes by
default. Add support for writing to clk_rate nodes via debugfs, this
basically adds a nice debugging capability for testing clk_set_rate
functionality directly from userspace. As this can be considered
dangerous, add a separate Kconfig entry for enabling this feature, and
make it default as not enabled.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/Kconfig |  9 +++++++++
 drivers/clk/clk.c   | 27 +++++++++++++++++++++++++++
 2 files changed, 36 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 801fa1cd0321..4815ed5248c5 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -23,6 +23,15 @@  config COMMON_CLK
 menu "Common Clock Framework"
 	depends on COMMON_CLK
 
+config COMMON_CLK_DEBUGFS_WRITE_ACCESS
+	bool "Clock debugfs write access enable"
+	depends on DEBUG_FS
+	default n
+	---help---
+	  Enables write access to debugfs entries. This is very useful
+	  for debugging purposes but can be dangerous, thus the default
+	  setting is n.
+
 config COMMON_CLK_WM831X
 	tristate "Clock driver for WM831x/2x PMICs"
 	depends on MFD_WM831X
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ca99e9db6575..b0e82193a63d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3093,6 +3093,28 @@  static int clk_duty_cycle_show(struct seq_file *s, void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle);
 
+#ifdef CONFIG_COMMON_CLK_DEBUGFS_WRITE_ACCESS
+static int clk_dbg_rate_get(void *data, u64 *val)
+{
+	struct clk_core *core = data;
+
+	*val = core->rate;
+
+	return 0;
+}
+
+static int clk_dbg_rate_set(void *data, u64 val)
+{
+	struct clk_core *core = data;
+
+	clk_core_set_rate_nolock(core, val);
+
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(clk_dbg_option_rate, clk_dbg_rate_get, clk_dbg_rate_set, "%llu\n");
+#endif
+
 static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
 {
 	struct dentry *root;
@@ -3103,7 +3125,12 @@  static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
 	root = debugfs_create_dir(core->name, pdentry);
 	core->dentry = root;
 
+#ifdef CONFIG_COMMON_CLK_DEBUGFS_WRITE_ACCESS
+	debugfs_create_file("clk_rate", 0644, root, core,
+			    &clk_dbg_option_rate);
+#else
 	debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
+#endif
 	debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
 	debugfs_create_u32("clk_phase", 0444, root, &core->phase);
 	debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);