| Message ID | 20191007122604.18508-3-t-kristo@ti.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: ti: fix GFX clocks for reset support | expand |
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 7ec8fe6aa7c1..af3e7805769e 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -73,7 +73,7 @@ static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = { }; static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { - { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, + { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" }, { 0 }, };
Due to the way ti sysc and hardreset line control is now implemented, it is not possible to poll the clock status for gfx clock independent of hardreset line control. Thus, add a flag to prevent handling this status bit from clock driver. Correct sequencing of events is guaranteed by ti-sysc bus driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> --- drivers/clk/ti/clk-43xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)