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[2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id j14sm9585014wrj.35.2019.10.27.09.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:18:17 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 5/5] ARM: dts: meson: provide the XTAL clock using a fixed-clock Date: Sun, 27 Oct 2019 17:18:05 +0100 Message-Id: <20191027161805.1176321-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> References: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The clock controller driver has provided the XTAL clock so far. This does not match how the hardware actually works because the XTAL clock is an actual crystal which is mounted on the PCB. Add the "xtal" clock to meson.dtsi and replace all references to the clock controller's CLKID_XTAL with the new xtal clock node. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson6.dtsi | 7 ------- arch/arm/boot/dts/meson8.dtsi | 15 ++++++++------- arch/arm/boot/dts/meson8b-ec100.dts | 2 +- arch/arm/boot/dts/meson8b-mxq.dts | 2 +- arch/arm/boot/dts/meson8b-odroidc1.dts | 2 +- arch/arm/boot/dts/meson8b.dtsi | 15 ++++++++------- 7 files changed, 26 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index c4447f6c8b2c..5d198309058a 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -282,4 +282,11 @@ }; }; }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 2d31b7ce3f8c..4716030a48d0 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -36,13 +36,6 @@ ranges = <0x0 0xd0000000 0x40000>; }; - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - clk81: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 5a7e3e5caebe..4f59a4c8f036 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -455,6 +455,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -529,8 +531,7 @@ &saradc { compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; - clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; amlogic,hhi-sysctrl = <&hhi>; nvmem-cells = <&temperature_calib>; @@ -548,31 +549,31 @@ }; &timer_abcde { - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk"; }; &uart_AO { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; clock-names = "baud", "xtal", "pclk"; }; &uart_A { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; clock-names = "baud", "xtal", "pclk"; }; &uart_B { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; clock-names = "baud", "xtal", "pclk"; }; &uart_C { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; clock-names = "baud", "xtal", "pclk"; }; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index bed1dfef1985..163a200d5a7b 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -377,7 +377,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts index 6e39ad52e42d..33037ef62d0a 100644 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ b/arch/arm/boot/dts/meson8b-mxq.dts @@ -165,7 +165,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index a24eccc354b9..a2a47804fc4a 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -340,7 +340,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 099bf8e711c9..1934666ff60f 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -434,6 +434,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -508,8 +510,7 @@ &saradc { compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; - clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; amlogic,hhi-sysctrl = <&hhi>; nvmem-cells = <&temperature_calib>; @@ -523,31 +524,31 @@ }; &timer_abcde { - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk"; }; &uart_AO { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; clock-names = "baud", "xtal", "pclk"; }; &uart_A { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; clock-names = "baud", "xtal", "pclk"; }; &uart_B { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; clock-names = "baud", "xtal", "pclk"; }; &uart_C { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; clock-names = "baud", "xtal", "pclk"; };