From patchwork Fri Nov 15 16:28:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11246733 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1FF0A13BD for ; Fri, 15 Nov 2019 16:29:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E9A4420740 for ; Fri, 15 Nov 2019 16:29:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bDwt676Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727552AbfKOQ3e (ORCPT ); Fri, 15 Nov 2019 11:29:34 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:36692 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727690AbfKOQ3d (ORCPT ); Fri, 15 Nov 2019 11:29:33 -0500 Received: by mail-pg1-f193.google.com with SMTP id k13so6248324pgh.3 for ; Fri, 15 Nov 2019 08:29:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zgqr5BSa48TxbTYLKMugnan1gSsGxic61qyv50u9LdE=; b=bDwt676ZHNZP4/OhuT46sME9F112AckEbHsVx2sEy47mcfLzQmbjlhL11cuUcDdaeM OiEVSvny1sL90sQ5WiTEfn2etLoNfRPQNv1Y2EB98oPolXEc9Z0/lo1M/Du5SZBFrzSg 6DefqqjTcwNku8DNOMJAoz/zgNAgj5C/U/XuvSRUEF8au2NcCv1SpQ2fuWCSbNLFNTx5 xAsoZSzAIV+HqrUGehN96r1kBlNsffXqGaD5fOs6JgTM2ZAfrlc+3nHLyX0aEd7NOiyL pxN2/U0DzY/jFCgrILutKYiJJky3xQi4Z5jKc990EwebB/EGdzxJSILWp9P5/ZFv5YXN r1rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Zgqr5BSa48TxbTYLKMugnan1gSsGxic61qyv50u9LdE=; b=RR46P7L+8JCAoD+3XzizryTgEWJUGTENchlum/iYbNHmyPjKbnzCHachzjfufDyQk2 Nn22nzi0zzoTJyMLuqZ+9KTlALyXKRlz4yD6i2FHHYzWOIr9j451MXo4Ct75PMNLq1// oID1qiYcclXp+V/+tr3G8LwLyG0UFhANaF6YToXxYRffqv+saWANnuh9BF0GHWU05/iv 1yXo4p1CJZu17g0obUBphvufcdQtg8S+lZU5rv96tv1ofgRuXH8RZAzCPbWZEmTxlqOj zi3PFS7Bf4I/gPwBU/RAQZZROxDAcYoJjaEs7UF2J//638Cwr7Yq5nBR5BatO/bgqcIE egtQ== X-Gm-Message-State: APjAAAXB2kSvz2DWXxnXDbh96JyG1kn+xqHPdpZ2CYGnknqMHH9dbz4r iqb4WkU2VqVyiyAoiacQC24Q X-Google-Smtp-Source: APXvYqwJum30njADesywZkB8CpZulCq0FtbSJmcjr9wllYN519fKElPQscgm6sU/4O6c76L7FXYGyQ== X-Received: by 2002:a63:715d:: with SMTP id b29mr17081495pgn.369.1573835370908; Fri, 15 Nov 2019 08:29:30 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6183:6d55:8418:2bbc:e6d8:2b4]) by smtp.gmail.com with ESMTPSA id y24sm12295288pfr.116.2019.11.15.08.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 08:29:30 -0800 (PST) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, fisher.cheng@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH v7 3/7] dt-bindings: clock: Add devicetree binding for BM1880 SoC Date: Fri, 15 Nov 2019 21:58:57 +0530 Message-Id: <20191115162901.17456-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191115162901.17456-1-manivannan.sadhasivam@linaro.org> References: <20191115162901.17456-1-manivannan.sadhasivam@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add YAML devicetree binding for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../bindings/clock/bitmain,bm1880-clk.yaml | 76 +++++++++++++++++ include/dt-bindings/clock/bm1880-clock.h | 82 +++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml create mode 100644 include/dt-bindings/clock/bm1880-clock.h diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml new file mode 100644 index 000000000000..e63827399c1a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 Clock Controller + +maintainers: + - Manivannan Sadhasivam + +description: | + The Bitmain BM1880 clock controller generates and supplies clock to + various peripherals within the SoC. + + This binding uses common clock bindings + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + const: bitmain,bm1880-clk + + reg: + items: + - description: pll registers + - description: system registers + + reg-names: + items: + - const: pll + - const: sys + + clocks: + maxItems: 1 + + clock-names: + const: osc + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + + # Example UART controller node that consumes clock generated by the clock controller: + - | + uart0: serial@58018000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk 45>, <&clk 46>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <0 9 4>; + reg-shift = <2>; + reg-io-width = <4>; + }; + +... diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h new file mode 100644 index 000000000000..b46732361b25 --- /dev/null +++ b/include/dt-bindings/clock/bm1880-clock.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Device Tree binding constants for Bitmain BM1880 SoC + * + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_BM1880_H +#define __DT_BINDINGS_CLOCK_BM1880_H + +#define BM1880_CLK_OSC 0 +#define BM1880_CLK_MPLL 1 +#define BM1880_CLK_SPLL 2 +#define BM1880_CLK_FPLL 3 +#define BM1880_CLK_DDRPLL 4 +#define BM1880_CLK_A53 5 +#define BM1880_CLK_50M_A53 6 +#define BM1880_CLK_AHB_ROM 7 +#define BM1880_CLK_AXI_SRAM 8 +#define BM1880_CLK_DDR_AXI 9 +#define BM1880_CLK_EFUSE 10 +#define BM1880_CLK_APB_EFUSE 11 +#define BM1880_CLK_AXI5_EMMC 12 +#define BM1880_CLK_EMMC 13 +#define BM1880_CLK_100K_EMMC 14 +#define BM1880_CLK_AXI5_SD 15 +#define BM1880_CLK_SD 16 +#define BM1880_CLK_100K_SD 17 +#define BM1880_CLK_500M_ETH0 18 +#define BM1880_CLK_AXI4_ETH0 19 +#define BM1880_CLK_500M_ETH1 20 +#define BM1880_CLK_AXI4_ETH1 21 +#define BM1880_CLK_AXI1_GDMA 22 +#define BM1880_CLK_APB_GPIO 23 +#define BM1880_CLK_APB_GPIO_INTR 24 +#define BM1880_CLK_GPIO_DB 25 +#define BM1880_CLK_AXI1_MINER 26 +#define BM1880_CLK_AHB_SF 27 +#define BM1880_CLK_SDMA_AXI 28 +#define BM1880_CLK_SDMA_AUD 29 +#define BM1880_CLK_APB_I2C 30 +#define BM1880_CLK_APB_WDT 31 +#define BM1880_CLK_APB_JPEG 32 +#define BM1880_CLK_JPEG_AXI 33 +#define BM1880_CLK_AXI5_NF 34 +#define BM1880_CLK_APB_NF 35 +#define BM1880_CLK_NF 36 +#define BM1880_CLK_APB_PWM 37 +#define BM1880_CLK_DIV_0_RV 38 +#define BM1880_CLK_DIV_1_RV 39 +#define BM1880_CLK_MUX_RV 40 +#define BM1880_CLK_RV 41 +#define BM1880_CLK_APB_SPI 42 +#define BM1880_CLK_TPU_AXI 43 +#define BM1880_CLK_DIV_UART_500M 44 +#define BM1880_CLK_UART_500M 45 +#define BM1880_CLK_APB_UART 46 +#define BM1880_CLK_APB_I2S 47 +#define BM1880_CLK_AXI4_USB 48 +#define BM1880_CLK_APB_USB 49 +#define BM1880_CLK_125M_USB 50 +#define BM1880_CLK_33K_USB 51 +#define BM1880_CLK_DIV_12M_USB 52 +#define BM1880_CLK_12M_USB 53 +#define BM1880_CLK_APB_VIDEO 54 +#define BM1880_CLK_VIDEO_AXI 55 +#define BM1880_CLK_VPP_AXI 56 +#define BM1880_CLK_APB_VPP 57 +#define BM1880_CLK_DIV_0_AXI1 58 +#define BM1880_CLK_DIV_1_AXI1 59 +#define BM1880_CLK_AXI1 60 +#define BM1880_CLK_AXI2 61 +#define BM1880_CLK_AXI3 62 +#define BM1880_CLK_AXI4 63 +#define BM1880_CLK_AXI5 64 +#define BM1880_CLK_DIV_0_AXI6 65 +#define BM1880_CLK_DIV_1_AXI6 66 +#define BM1880_CLK_MUX_AXI6 67 +#define BM1880_CLK_AXI6 68 +#define BM1880_NR_CLKS 69 + +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */