| Message ID | 20191122235622.8818-2-michael@walle.cc (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [1/2] dt-bindings: clock: document the fsl-sai driver | expand |
Hi, Am 2019-11-23 00:56, schrieb Michael Walle: > With this driver it is possible to use the BCLK pin of the SAI module > as > a generic clock output. This is esp. useful if you want to drive a > clock > to an audio codec. Because the output only allows integer divider > values > the audio codec needs an integrated PLL. ping :) will someone pull this driver? Or have any remarks? Here is the board what would use this driver: https://lore.kernel.org/linux-devicetree/20191123201317.25861-5-michael@walle.cc/ -michael > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > drivers/clk/Kconfig | 12 ++++++ > drivers/clk/Makefile | 1 + > drivers/clk/clk-fsl-sai.c | 84 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 97 insertions(+) > create mode 100644 drivers/clk/clk-fsl-sai.c > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index c44247d0b83e..d3bd43e8a912 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -167,6 +167,18 @@ config COMMON_CLK_CS2000_CP > help > If you say yes here you get support for the CS2000 clock > multiplier. > > +config COMMON_CLK_FSL_SAI > + bool "Clock driver for BCLK of Freescale SAI cores" > + depends on ARCH_LAYERSCAPE || COMPILE_TEST > + help > + This driver supports the Freescale SAI (Synchronous Audio > Interface) > + to be used as a generic clock output. Some SoCs have restrictions > + regarding the possible pin multiplexer settings. Eg. on some SoCs > + two SAI interfaces can only be enabled together. If just one is > + needed, the BCLK pin of the second one can be used as general > + purpose clock output. Ideally, it can be used to drive an audio > + codec (sometimes known as MCLK). > + > config COMMON_CLK_GEMINI > bool "Clock driver for Cortina Systems Gemini SoC" > depends on ARCH_GEMINI || COMPILE_TEST > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 0138fb14e6f8..139f55e544a8 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o > obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o > obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o > obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o > +obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o > obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o > obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o > obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o > diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c > new file mode 100644 > index 000000000000..b92054d15ab1 > --- /dev/null > +++ b/drivers/clk/clk-fsl-sai.c > @@ -0,0 +1,84 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Freescale SAI BCLK as a generic clock driver > + * > + * Copyright 2019 Kontron Europe GmbH > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/err.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/slab.h> > + > +#define I2S_CSR 0x00 > +#define I2S_CR2 0x08 > +#define CSR_BCE_BIT 28 > +#define CR2_BCD BIT(24) > +#define CR2_DIV_SHIFT 0 > +#define CR2_DIV_WIDTH 8 > + > +struct fsl_sai_clk { > + struct clk_divider div; > + struct clk_gate gate; > + spinlock_t lock; > +}; > + > +static void __init fsl_sai_clk_setup(struct device_node *node) > +{ > + const char *clk_name = node->name; > + struct fsl_sai_clk *sai_clk; > + unsigned int num_parents; > + const char *parent_name; > + void __iomem *base; > + struct clk_hw *hw; > + > + num_parents = of_clk_get_parent_count(node); > + if (!num_parents) { > + pr_err("%s: no parent found", clk_name); > + return; > + } > + > + parent_name = of_clk_get_parent_name(node, 0); > + > + sai_clk = kzalloc(sizeof(*sai_clk), GFP_KERNEL); > + if (!sai_clk) > + return; > + > + base = of_iomap(node, 0); > + if (base == NULL) { > + pr_err("%s: failed to map register space", clk_name); > + goto err; > + } > + > + spin_lock_init(&sai_clk->lock); > + > + sai_clk->gate.reg = base + I2S_CSR; > + sai_clk->gate.bit_idx = CSR_BCE_BIT; > + sai_clk->gate.lock = &sai_clk->lock; > + > + sai_clk->div.reg = base + I2S_CR2; > + sai_clk->div.shift = CR2_DIV_SHIFT; > + sai_clk->div.width = CR2_DIV_WIDTH; > + sai_clk->div.lock = &sai_clk->lock; > + > + /* set clock direction, we are the BCLK master */ > + writel(CR2_BCD, base + I2S_CR2); > + > + hw = clk_hw_register_composite(NULL, clk_name, &parent_name, 1, > + NULL, NULL, > + &sai_clk->div.hw, &clk_divider_ops, > + &sai_clk->gate.hw, &clk_gate_ops, > + CLK_SET_RATE_GATE); > + if (IS_ERR(hw)) > + goto err; > + > + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); > + > + return; > + > +err: > + kfree(sai_clk); > +} > + > +CLK_OF_DECLARE(fsl_sai_clk, "fsl,vf610-sai-clock", fsl_sai_clk_setup);
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c44247d0b83e..d3bd43e8a912 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -167,6 +167,18 @@ config COMMON_CLK_CS2000_CP help If you say yes here you get support for the CS2000 clock multiplier. +config COMMON_CLK_FSL_SAI + bool "Clock driver for BCLK of Freescale SAI cores" + depends on ARCH_LAYERSCAPE || COMPILE_TEST + help + This driver supports the Freescale SAI (Synchronous Audio Interface) + to be used as a generic clock output. Some SoCs have restrictions + regarding the possible pin multiplexer settings. Eg. on some SoCs + two SAI interfaces can only be enabled together. If just one is + needed, the BCLK pin of the second one can be used as general + purpose clock output. Ideally, it can be used to drive an audio + codec (sometimes known as MCLK). + config COMMON_CLK_GEMINI bool "Clock driver for Cortina Systems Gemini SoC" depends on ARCH_GEMINI || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0138fb14e6f8..139f55e544a8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o +obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c new file mode 100644 index 000000000000..b92054d15ab1 --- /dev/null +++ b/drivers/clk/clk-fsl-sai.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Freescale SAI BCLK as a generic clock driver + * + * Copyright 2019 Kontron Europe GmbH + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/slab.h> + +#define I2S_CSR 0x00 +#define I2S_CR2 0x08 +#define CSR_BCE_BIT 28 +#define CR2_BCD BIT(24) +#define CR2_DIV_SHIFT 0 +#define CR2_DIV_WIDTH 8 + +struct fsl_sai_clk { + struct clk_divider div; + struct clk_gate gate; + spinlock_t lock; +}; + +static void __init fsl_sai_clk_setup(struct device_node *node) +{ + const char *clk_name = node->name; + struct fsl_sai_clk *sai_clk; + unsigned int num_parents; + const char *parent_name; + void __iomem *base; + struct clk_hw *hw; + + num_parents = of_clk_get_parent_count(node); + if (!num_parents) { + pr_err("%s: no parent found", clk_name); + return; + } + + parent_name = of_clk_get_parent_name(node, 0); + + sai_clk = kzalloc(sizeof(*sai_clk), GFP_KERNEL); + if (!sai_clk) + return; + + base = of_iomap(node, 0); + if (base == NULL) { + pr_err("%s: failed to map register space", clk_name); + goto err; + } + + spin_lock_init(&sai_clk->lock); + + sai_clk->gate.reg = base + I2S_CSR; + sai_clk->gate.bit_idx = CSR_BCE_BIT; + sai_clk->gate.lock = &sai_clk->lock; + + sai_clk->div.reg = base + I2S_CR2; + sai_clk->div.shift = CR2_DIV_SHIFT; + sai_clk->div.width = CR2_DIV_WIDTH; + sai_clk->div.lock = &sai_clk->lock; + + /* set clock direction, we are the BCLK master */ + writel(CR2_BCD, base + I2S_CR2); + + hw = clk_hw_register_composite(NULL, clk_name, &parent_name, 1, + NULL, NULL, + &sai_clk->div.hw, &clk_divider_ops, + &sai_clk->gate.hw, &clk_gate_ops, + CLK_SET_RATE_GATE); + if (IS_ERR(hw)) + goto err; + + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + return; + +err: + kfree(sai_clk); +} + +CLK_OF_DECLARE(fsl_sai_clk, "fsl,vf610-sai-clock", fsl_sai_clk_setup);
With this driver it is possible to use the BCLK pin of the SAI module as a generic clock output. This is esp. useful if you want to drive a clock to an audio codec. Because the output only allows integer divider values the audio codec needs an integrated PLL. Signed-off-by: Michael Walle <michael@walle.cc> --- drivers/clk/Kconfig | 12 ++++++ drivers/clk/Makefile | 1 + drivers/clk/clk-fsl-sai.c | 84 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 drivers/clk/clk-fsl-sai.c