| Message ID | 20191206134202.18784-6-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | spi: Add Renesas SPIBSC controller | expand |
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 72b79770e336..05c310c57c11 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -68,6 +68,17 @@ cache-level = <2>; }; + spibsc: spi@1f800000 { + compatible = "renesas,r7s9210-spibsc", "renesas,spibsc"; + reg = <0x1f800000 0x100>, <0x20000000 0x10000000>; + clocks = <&cpg CPG_MOD 83>; + power-domains = <&cpg>; + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e8007000 { compatible = "renesas,scif-r7s9210"; reg = <0xe8007000 0x18>;
Add SPIBSC Device support for RZ/A2. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- v2: * Changed reg range from 0x8c to 0x100 * Added interrupts property --- arch/arm/boot/dts/r7s9210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)