From patchwork Fri Jan 24 22:42:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC8AC1398 for ; Fri, 24 Jan 2020 22:43:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B5ED20838 for ; Fri, 24 Jan 2020 22:43:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="W+AWfGtY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387427AbgAXWnZ (ORCPT ); Fri, 24 Jan 2020 17:43:25 -0500 Received: from mail-pg1-f169.google.com ([209.85.215.169]:42652 "EHLO mail-pg1-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387429AbgAXWnU (ORCPT ); Fri, 24 Jan 2020 17:43:20 -0500 Received: by mail-pg1-f169.google.com with SMTP id s64so1844639pgb.9 for ; Fri, 24 Jan 2020 14:43:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fR36UAT87Z0TKgzJqLSUdRVGW5KC0xvFs4pz6EoaSEs=; b=W+AWfGtYERngYx58+JdIqakd2DAkpetfVaeID9hwBCBbON7jnjF1idcPZDN1OLhN3w 622xZcGgQxsvPHvZRkgWq4dOLsTOXwAZNJpdMf7SjRPUPWSR5XzyvfIPtF37IF8PcLyF eG2poAj44PWrspC186mA54CivpdLZzf8SEW8k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fR36UAT87Z0TKgzJqLSUdRVGW5KC0xvFs4pz6EoaSEs=; b=jsyj+Utzemoiiec/t0aSN+jsjamloxVKUVpsGpOgX5phoMjDGrM5T7sy3tS3d2YqUc c7qqmnD5ChCNsQZxTiQU+O+ddvc86Q8x+fBBxQhgseXuazlhIWYLoTLuniTPjbK0snlb nT9ixKTDKEM0gWPmKeTKpBFQmaY/SyySS6OJLeGrPHFEpHUS4c8NYJR6KS2WqOA2IOnu kOb+N8pP37nFWasLicuyTBTHlDWLUQGFjmLyQid47oUEBl8AH/k1DyPkQdtRuSHltE7p kJad55MdRJLEHEUN0wCq7AChmEFfeMcJvZc6LOyttAttdpeSJDbZ04EySerDbsjvlmL8 4vqw== X-Gm-Message-State: APjAAAVmYtqqRG7fmii4iK31cUCYArLo+9lkdTo0bOp9CmKhIX+w1QzL /fuAAxF7zSkoJzYIoILYuhYdbQ== X-Google-Smtp-Source: APXvYqzQWhWF4MQsZ7Z+9Immx0ruH/IjtEERzHTTTIJYCcURTdVPjfvN5BCLXulZMP1xLv21An1JIQ== X-Received: by 2002:a63:1a19:: with SMTP id a25mr6709867pga.447.1579905800195; Fri, 24 Jan 2020 14:43:20 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:19 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 04/10] dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998 Date: Fri, 24 Jan 2020 14:42:19 -0800 Message-Id: <20200124144154.v2.4.I513cd73b16665065ae6c22cf594d8b543745e28c@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The qcom,dispcc bindings had a few problems with them: 1. When things were converted to yaml the name of the "gpll0 main" clock got changed from "gpll0" to "gpll0_main". Change it back. 2. The bindings are written so that new boards don't have to specify all the clocks. That doesn't really make sense. Make it so that on new boards all 3 clocks are required. This also updates the example to be sc7180 and use symbolic names for clock indicies. NOTE: It seems that we can only make things _more_ restrictive in the per-SoC overrides for minItems/maxItems. ...so by default we start out with a loose min=2, max=3 (implicit). Then we restrict msm8998 to exactly 2 and everything else to exactly 3. Fixes: 5c6f3a36b913 ("dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("dt-bindings: clock: Fix qcom,gpucc...") new for v2. .../devicetree/bindings/clock/qcom,gpucc.yaml | 42 ++++++++++++++----- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 622845aa643f..64cf3c450325 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -21,19 +21,17 @@ properties: - qcom,sdm845-gpucc clocks: - minItems: 1 - maxItems: 3 + minItems: 2 items: - description: Board XO source - - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src) - - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src) + - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src) + - description: GPLL0 div branch source (gcc_gpu_gpll0_div_clk_src) clock-names: - minItems: 1 - maxItems: 3 + minItems: 2 items: - const: xo - - const: gpll0_main + - const: gpll0 - const: gpll0_div '#clock-cells': @@ -57,16 +55,38 @@ required: - '#reset-cells' - '#power-domain-cells' +if: + properties: + compatible: + contains: + const: qcom,msm8998-gpucc +then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 +else: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + examples: # Example of GPUCC with clock node properties for SDM845: - | + #include + #include clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; - reg = <0x5090000 0x9000>; - clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>; - clock-names = "xo", "gpll0_main", "gpll0_div"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "xo", "gpll0", "gpll0_div"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - }; + }; ...