From patchwork Fri Jan 24 22:42:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11351203 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9449E1398 for ; Fri, 24 Jan 2020 22:43:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72D4D2071E for ; Fri, 24 Jan 2020 22:43:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="MDjGZDMX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387475AbgAXWnn (ORCPT ); Fri, 24 Jan 2020 17:43:43 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:34547 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387458AbgAXWnY (ORCPT ); Fri, 24 Jan 2020 17:43:24 -0500 Received: by mail-pl1-f193.google.com with SMTP id q13so1375160pls.1 for ; Fri, 24 Jan 2020 14:43:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=azOJGeenO90UDElVZnGvhTa1WOYkaMQED3kOM1E619Q=; b=MDjGZDMXlqXZUfV7OZldyntXHGM87aWp1WZpVtZvG3lp15ahEHyRkexF4mzQJ7dlAO x6rNvYucK03/VVjtUAEO2qx3vBAUWWaA+UmqKnUXMcCJCaZmqlqcLHf8XYJi6MqwO7RA Iu9IohHaGiWj+pwqnMctsCsTFYvH2hg9ofjp0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=azOJGeenO90UDElVZnGvhTa1WOYkaMQED3kOM1E619Q=; b=LP9lCR3M6tc/UDC+XZE5AsW8+aqiA9Yy2I0jJZ8yO2dCmy6U84IeqLQ4ez6oSmGjMT /VqdRTexmxRGLFmwYX1MKygMg0lMkmYno2U5Zvb3d0MNmVH8XoY3Ww6u6VGxbIVJix9H lj5ItUSN8qGR4Dyhoym+BSd3rRA6/johCyrBwtdi6umOXVHSXH1h1Ejjo2vI3uUxCq4b KfvowI65t4Gwy5A22WAkpr9mOdsOOexuUYbBhmhXN5d3grJj6NIC+sMGhDoom/nZ+2KV UBmhv5vo+bWavaifsJPCzHR8fMbbvcTm6HwfpyOeY2LSVDmI2WHY2nIInxHVEBVTypFP fYRw== X-Gm-Message-State: APjAAAWyJOQaOSIz4YXSwCb/sllyvp0qilnWZGq8rR603c6gh84ZLDOx Lq/5jUQiXdkBYMh628PRXwMFrA== X-Google-Smtp-Source: APXvYqxYRZKxhf678NfYnON6C+bRqFB77arOwAg3WMS1KXZ4+qWQqA43m9A0cMWuZMS04lt6xPrTBQ== X-Received: by 2002:a17:902:7009:: with SMTP id y9mr6022788plk.254.1579905803606; Fri, 24 Jan 2020 14:43:23 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:23 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 07/10] clk: qcom: Fix sc7180 gpucc parent data Date: Fri, 24 Jan 2020 14:42:22 -0800 Message-Id: <20200124144154.v2.7.I3bf44e33f4dc7ecca10a50dbccb7dc082894fa59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The bindings file (qcom,gpucc.yaml) does not agree with the names we use for input clocks. Fix us. This takes into account the changes in the recent patch ("dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998"), but even without that patch the names in the driver were still not right. Since we didn't add the "test" clock to the bindings (apparently it's never used), kill it from the driver. If someone has a use for it we should add it to the bindings and bring it back. Instead of updating the size of the array now that the test clock is gone, switch to using the less error-prone ARRAY_SIZE. Not sure why it didn't always use that. Fixes: 745ff069a49c ("clk: qcom: Add graphics clock controller driver for SC7180") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("clk: qcom: Fix sc7180 gpucc parent data") new for v2. drivers/clk/qcom/gpucc-sc7180.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index ec61194cceaf..da56506036e2 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -47,7 +47,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll1", .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", + .fw_name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, @@ -64,11 +64,10 @@ static const struct parent_map gpu_cc_parent_map_0[] = { }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, + { .fw_name = "xo" }, { .hw = &gpu_cc_pll1.clkr.hw }, - { .fw_name = "gcc_gpu_gpll0_clk_src" }, - { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "gpll0" }, + { .fw_name = "gpll0_div" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { @@ -86,7 +85,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .parent_data = gpu_cc_parent_data_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, },