From patchwork Fri Jan 24 23:20:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 11351315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9898F1580 for ; Fri, 24 Jan 2020 23:28:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 80C232081E for ; Fri, 24 Jan 2020 23:28:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729592AbgAXX2Z (ORCPT ); Fri, 24 Jan 2020 18:28:25 -0500 Received: from mailoutvs37.siol.net ([185.57.226.228]:38357 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729598AbgAXX2Z (ORCPT ); Fri, 24 Jan 2020 18:28:25 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTP id C2796522844; Sat, 25 Jan 2020 00:20:30 +0100 (CET) X-Virus-Scanned: amavisd-new at psrvmta12.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id oCHcyPFtp5FI; Sat, 25 Jan 2020 00:20:30 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTPS id 5DDB8522899; Sat, 25 Jan 2020 00:20:30 +0100 (CET) Received: from localhost.localdomain (cpe-194-152-20-232.static.triera.net [194.152.20.232]) (Authenticated sender: 031275009) by mail.siol.net (Zimbra) with ESMTPSA id 03FC6522844; Sat, 25 Jan 2020 00:20:28 +0100 (CET) From: Jernej Skrabec To: mripard@kernel.org, wens@csie.org Cc: mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, sboyd@kernel.org, hverkuil-cisco@xs4all.nl, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 2/8] clk: sunxi-ng: sun8i-de2: Fix A83T clocks and reset Date: Sat, 25 Jan 2020 00:20:08 +0100 Message-Id: <20200124232014.574989-3-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200124232014.574989-1-jernej.skrabec@siol.net> References: <20200124232014.574989-1-jernej.skrabec@siol.net> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org A83T also contains rotation core, but related clocks and reset are missing. Add them. With that fixed, H3 and V3s capabilities no longer match (they don't have rotation core), so create new struct for them. Signed-off-by: Jernej Skrabec --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 31 ++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 08074d935317..800659cf7347 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -50,6 +50,8 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4, CLK_SET_RATE_PARENT); static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, CLK_SET_RATE_PARENT); +static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4, + CLK_SET_RATE_PARENT); static struct ccu_common *sun50i_a64_de2_clks[] = { &mixer0_clk.common, @@ -81,6 +83,10 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = { &mixer0_div_a83_clk.common, &mixer1_div_a83_clk.common, &wb_div_a83_clk.common, + + &bus_rot_clk.common, + &rot_clk.common, + &rot_div_a83_clk.common, }; static struct ccu_common *sun8i_h3_de2_clks[] = { @@ -113,16 +119,19 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { [CLK_MIXER0] = &mixer0_clk.common.hw, [CLK_MIXER1] = &mixer1_clk.common.hw, [CLK_WB] = &wb_clk.common.hw, + [CLK_ROT] = &rot_clk.common.hw, [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, [CLK_BUS_WB] = &bus_wb_clk.common.hw, + [CLK_BUS_ROT] = &bus_rot_clk.common.hw, [CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw, [CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw, [CLK_WB_DIV] = &wb_div_a83_clk.common.hw, + [CLK_ROT_DIV] = &rot_div_a83_clk.common.hw, }, - .num = CLK_NUMBER_WITHOUT_ROT, + .num = CLK_NUMBER_WITH_ROT, }; static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = { @@ -179,8 +188,18 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = { static struct ccu_reset_map sun8i_a83t_de2_resets[] = { [RST_MIXER0] = { 0x08, BIT(0) }, /* - * For A83T, H3 and R40, mixer1 reset line is shared with wb, so + * A83T and R40 mixer1 reset line is shared with wb, so * only RST_WB is exported here. + */ + [RST_WB] = { 0x08, BIT(2) }, + [RST_ROT] = { 0x08, BIT(3) }, +}; + +static struct ccu_reset_map sun8i_h3_de2_resets[] = { + [RST_MIXER0] = { 0x08, BIT(0) }, + /* + * H3 mixer1 reset line is shared with wb, so only RST_WB + * is exported here. * For V3s there's just no mixer1, so it also shares this struct. */ [RST_WB] = { 0x08, BIT(2) }, @@ -215,8 +234,8 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { .hw_clks = &sun8i_h3_de2_hw_clks, - .resets = sun8i_a83t_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + .resets = sun8i_h3_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets), }; static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { @@ -245,8 +264,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { .hw_clks = &sun8i_v3s_de2_hw_clks, - .resets = sun8i_a83t_de2_resets, - .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), + .resets = sun8i_h3_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_de2_resets), }; static int sunxi_de2_clk_probe(struct platform_device *pdev)