| Message ID | 20200211030813.13992-1-festevam@gmail.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [1/2] clk: imx8mm: Fix the CLKO1 source select list | expand |
On 20-02-11 00:08:12, Fabio Estevam wrote: > The CLKO1 clock source select list is the following as per the i.MX8MM > Reference Manual (put in increasing order): > > 000 - 24M_REF_CLK > 001 - SYSTEM_PLL1_CLK > 010 - None > 011 - SYSTEM_PLL1_DIV4 > 100 - AUDIO_PLL2_CLK > 101 - SYSTEM_PLL2_DIV2 > 110 - VPU_PLL_CLK > 111 - SYSTEM_PLL1_DIV10 > > Fix it accordingly. > > Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") > Signed-off-by: Fabio Estevam <festevam@gmail.com> For both patches: Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/clk-imx8mm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c > index 2ed93fc25087..770cf2ae58aa 100644 > --- a/drivers/clk/imx/clk-imx8mm.c > +++ b/drivers/clk/imx/clk-imx8mm.c > @@ -283,8 +283,8 @@ static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8 > > static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; > > -static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_out", > - "vpu_pll", "sys_pll1_80m", }; > +static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m", > + "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", }; > > static struct clk_hw_onecell_data *clk_hw_data; > static struct clk_hw **hws; > -- > 2.17.1 >
On Tue, Feb 11, 2020 at 12:08:12AM -0300, Fabio Estevam wrote: > The CLKO1 clock source select list is the following as per the i.MX8MM > Reference Manual (put in increasing order): > > 000 - 24M_REF_CLK > 001 - SYSTEM_PLL1_CLK > 010 - None > 011 - SYSTEM_PLL1_DIV4 > 100 - AUDIO_PLL2_CLK > 101 - SYSTEM_PLL2_DIV2 > 110 - VPU_PLL_CLK > 111 - SYSTEM_PLL1_DIV10 > > Fix it accordingly. > > Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") > Signed-off-by: Fabio Estevam <festevam@gmail.com> Applied both, thanks.
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 2ed93fc25087..770cf2ae58aa 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -283,8 +283,8 @@ static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8 static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; -static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_out", - "vpu_pll", "sys_pll1_80m", }; +static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m", + "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", }; static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws;
The CLKO1 clock source select list is the following as per the i.MX8MM Reference Manual (put in increasing order): 000 - 24M_REF_CLK 001 - SYSTEM_PLL1_CLK 010 - None 011 - SYSTEM_PLL1_DIV4 100 - AUDIO_PLL2_CLK 101 - SYSTEM_PLL2_DIV2 110 - VPU_PLL_CLK 111 - SYSTEM_PLL1_DIV10 Fix it accordingly. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Fabio Estevam <festevam@gmail.com> --- drivers/clk/imx/clk-imx8mm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)