diff mbox series

[v2,3/7] clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core

Message ID 20200211185936.245174-4-jernej.skrabec@siol.net (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: sunxi-ng: sun8i-de2: Multiple fixes | expand

Commit Message

Jernej Škrabec Feb. 11, 2020, 6:59 p.m. UTC 
DE3 documentation regarding presence of rotate core in H6 is a bit
confusing. Register descriptions mention bits for enabling rotate core
clocks and reset, but general overview doesn't list it as feature of H6
display engine, BSP kernel doesn't support it and there is no interrupt
listed for it. Manual poking registers also didn't reveal presence of
rotate core.

Let's assume there isn't any rotate core on H6 present and remove
related clocks. With that done, structures are same as those for H5, so
just reuse H5 structure.

Fixes: 56808da9f97f ("clk: sunxi-ng: Add support for H6 DE3 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 57 +---------------------------
 1 file changed, 1 insertion(+), 56 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index c6220be8e205..87a30d072ae9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -51,24 +51,6 @@  static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
 static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
 		   CLK_SET_RATE_PARENT);
 
-static struct ccu_common *sun50i_h6_de3_clks[] = {
-	&mixer0_clk.common,
-	&mixer1_clk.common,
-	&wb_clk.common,
-
-	&bus_mixer0_clk.common,
-	&bus_mixer1_clk.common,
-	&bus_wb_clk.common,
-
-	&mixer0_div_clk.common,
-	&mixer1_div_clk.common,
-	&wb_div_clk.common,
-
-	&bus_rot_clk.common,
-	&rot_clk.common,
-	&rot_div_clk.common,
-};
-
 static struct ccu_common *sun8i_a83t_de2_clks[] = {
 	&mixer0_clk.common,
 	&mixer1_clk.common,
@@ -194,26 +176,6 @@  static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
 	.num	= CLK_NUMBER_WITH_ROT,
 };
 
-static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
-	.hws	= {
-		[CLK_MIXER0]		= &mixer0_clk.common.hw,
-		[CLK_MIXER1]		= &mixer1_clk.common.hw,
-		[CLK_WB]		= &wb_clk.common.hw,
-		[CLK_ROT]		= &rot_clk.common.hw,
-
-		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
-		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
-		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
-		[CLK_BUS_ROT]		= &bus_rot_clk.common.hw,
-
-		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
-		[CLK_MIXER1_DIV]	= &mixer1_div_clk.common.hw,
-		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
-		[CLK_ROT_DIV]		= &rot_div_clk.common.hw,
-	},
-	.num	= CLK_NUMBER_WITH_ROT,
-};
-
 static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
 	[RST_MIXER0]	= { 0x08, BIT(0) },
 	/*
@@ -237,13 +199,6 @@  static struct ccu_reset_map sun50i_h5_de2_resets[] = {
 	[RST_WB]	= { 0x08, BIT(2) },
 };
 
-static struct ccu_reset_map sun50i_h6_de3_resets[] = {
-	[RST_MIXER0]	= { 0x08, BIT(0) },
-	[RST_MIXER1]	= { 0x08, BIT(1) },
-	[RST_WB]	= { 0x08, BIT(2) },
-	[RST_ROT]	= { 0x08, BIT(3) },
-};
-
 static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
 	.ccu_clks	= sun8i_a83t_de2_clks,
 	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_de2_clks),
@@ -284,16 +239,6 @@  static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
 	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
 };
 
-static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
-	.ccu_clks	= sun50i_h6_de3_clks,
-	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_de3_clks),
-
-	.hw_clks	= &sun50i_h6_de3_hw_clks,
-
-	.resets		= sun50i_h6_de3_resets,
-	.num_resets	= ARRAY_SIZE(sun50i_h6_de3_resets),
-};
-
 static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
 	.ccu_clks	= sun8i_v3s_de2_clks,
 	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_de2_clks),
@@ -406,7 +351,7 @@  static const struct of_device_id sunxi_de2_clk_ids[] = {
 	},
 	{
 		.compatible = "allwinner,sun50i-h6-de3-clk",
-		.data = &sun50i_h6_de3_clk_desc,
+		.data = &sun50i_h5_de2_clk_desc,
 	},
 	{ }
 };