From patchwork Tue May 12 18:16:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11543725 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53C06186E for ; Tue, 12 May 2020 18:17:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 301F420836 for ; Tue, 12 May 2020 18:17:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1589307439; bh=SH4TNKWiiMK8Bi96neyAYYKhQf6TWRQT/RGdYI++BQY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=IhkK3HS58WsmM+17D72ahAzN+NI5P2ZZ/ulzJcj0IfWAjrtHXHY/Q0cKD8w59k8BJ kGaOE+jo6lZLioNHWDE7Us244nkI8BpS+qsLATFrtjYo2BmQa4PRD7Rmc3dM/+Ioqy JGG+MERIe1JfLZ3qix6aDMmBBej3QluHFV2ikEOo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730610AbgELSRC (ORCPT ); Tue, 12 May 2020 14:17:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:57268 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730200AbgELSRC (ORCPT ); Tue, 12 May 2020 14:17:02 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id EDC1620733; Tue, 12 May 2020 18:17:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1589307421; bh=SH4TNKWiiMK8Bi96neyAYYKhQf6TWRQT/RGdYI++BQY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XRJJ8Qu2KupTZV05XmZVjD5bYb9CxKYGp7LfXo/Pv0DHGMTfj2kBpYx53jp7BiHYQ wd+2Apw3HiN4Yp5uqNoe6HzzHZObBvixMq7ffUB3b8nu+RNewlKrWHwguPC0id9YKQ ipFjN2RlGUJVIbTt1g1q4NjpndzrFlLOI8Y48Ve8= From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com Subject: [RESEND PATCHv7 3/5] clk: socfpga: add const to _ops data structures Date: Tue, 12 May 2020 13:16:45 -0500 Message-Id: <20200512181647.5071-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200512181647.5071-1-dinguyen@kernel.org> References: <20200512181647.5071-1-dinguyen@kernel.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All the static clk_ops data structure need a const. Signed-off-by: Dinh Nguyen --- v7: no changes v6: no changes v5: no changes v4: no changes v3: no changes v2: created --- drivers/clk/socfpga/clk-pll-a10.c | 2 +- drivers/clk/socfpga/clk-pll-s10.c | 4 ++-- drivers/clk/socfpga/clk-pll.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 6d9395106c0c..db54f7d806a0 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -58,7 +58,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk) CLK_MGR_PLL_CLK_SRC_MASK; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, }; diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index 9faa80ff3b53..5c3e1ee44f6b 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -98,13 +98,13 @@ static int clk_pll_prepare(struct clk_hw *hwclk) return 0; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, .prepare = clk_pll_prepare, }; -static struct clk_ops clk_boot_ops = { +static const struct clk_ops clk_boot_ops = { .recalc_rate = clk_boot_clk_recalc_rate, .get_parent = clk_boot_get_parent, .prepare = clk_pll_prepare, diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index a001641b2f42..e5fb786843f3 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -65,7 +65,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk) CLK_MGR_PLL_CLK_SRC_MASK; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, };