Message ID | 20200723074112.3159-2-luca@lucaceresoli.net (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | dt-bindings: clk: versaclock5: change maintainer, convert to yaml, typo | expand |
Quoting Luca Ceresoli (2020-07-23 00:41:10) > 'idt' is misspelled 'itd' in a few places, fix it. > > Fixes: 34662f6e3084 ("dt: Add additional option bindings for IDT VersaClock") > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> > Reviewed-by: Rob Herring <robh@kernel.org> > > --- Applied to clk-next
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt index 6165b6ddb1a9..9656d4cf221c 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt @@ -35,7 +35,7 @@ For all output ports, a corresponding, optional child node named OUT1, OUT2, etc. can represent a each output, and the node can be used to specify the following: -- itd,mode: can be one of the following: +- idt,mode: can be one of the following: - VC5_LVPECL - VC5_CMOS - VC5_HCSL33 @@ -106,7 +106,7 @@ i2c-master-node { clock-names = "xin"; OUT1 { - itd,mode = <VC5_CMOS>; + idt,mode = <VC5_CMOS>; idt,voltage-microvolts = <1800000>; idt,slew-percent = <80>; };