diff mbox series

clk: imx: fix composite peripheral flags

Message ID 20200826071407.10543-1-peng.fan@nxp.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: imx: fix composite peripheral flags | expand

Commit Message

Peng Fan Aug. 26, 2020, 7:14 a.m. UTC
From: Peng Fan <peng.fan@nxp.com>

According to RM, for peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".

So we must have CLK_SET_PARENT_GATE flag to avoid glitch.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Shawn Guo Sept. 5, 2020, 1:35 a.m. UTC | #1
On Wed, Aug 26, 2020 at 03:14:07PM +0800, peng.fan@nxp.com wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> According to RM, for peripheral clock slice,
> "IP clock slices must be stopped to change the clock source.".
> 
> So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied, thanks.
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 78fb7e52a42a..2c309e3dc8e3 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -216,6 +216,7 @@  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->width = PCG_PREDIV_WIDTH;
 		divider_ops = &imx8m_clk_composite_divider_ops;
 		mux_ops = &clk_mux_ops;
+		flags |= CLK_SET_PARENT_GATE;
 	}
 
 	div->lock = &imx_ccm_lock;