[1/2] clk: qoriq: modify MAX_PLL_DIV to 32

Commit Message

Qiang Zhao Sept. 16, 2020, 3:03 a.m. UTC

From: Zhao Qiang <[e-mail]>

On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <[e-mail]>
---
 drivers/clk/clk-qoriq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Stephen Boyd Oct. 14, 2020, 2:48 a.m. UTC | #1

Quoting Qiang Zhao (2020-09-15 20:03:10)
> From: Zhao Qiang <[e-mail]>
> 
> On LS2088A, Watchdog need clk divided by 32,
> so modify MAX_PLL_DIV to 32
> 
> Signed-off-by: Zhao Qiang <[e-mail]>
> ---

Applied to clk-next

Patch

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e98..46101c6 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@ 
 #define CGA_PLL4	4	/* only on clockgen-1.0, which lacks CGB */
 #define CGB_PLL1	4
 #define CGB_PLL2	5
-#define MAX_PLL_DIV	16
+#define MAX_PLL_DIV	32
 
 struct clockgen_pll_div {
 	struct clk *clk;