[03/12] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu

Message ID	20201116075532.4019252-4-m.tretter@pengutronix.de (mailing list archive)
State	Not Applicable, archived
Headers	show Return-Path: <linux-clk-owner@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 810722222E From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com, rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de, robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, Michael Tretter <m.tretter@pengutronix.de> Date: Mon, 16 Nov 2020 08:55:23 +0100 Message-Id: <20201116075532.4019252-4-m.tretter@pengutronix.de> In-Reply-To: <20201116075532.4019252-1-m.tretter@pengutronix.de> References: <20201116075532.4019252-1-m.tretter@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [PATCH 03/12] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Precedence: bulk
Series	[01/12] ARM: dts: define indexes for output clocks \| expand [01/12] ARM: dts: define indexes for output clocks [02/12] clk: divider: fix initialization with parent_hw [03/12] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu [04/12] soc: xilinx: vcu: add helper to wait for PLL locked [05/12] soc: xilinx: vcu: add helpers for configuring PLL [06/12] soc: xilinx: vcu: implement PLL disable [07/12] soc: xilinx: vcu: register PLL as fixed rate clock [08/12] soc: xilinx: vcu: implement clock provider for output clocks [09/12] soc: xilinx: vcu: make pll post divider explicit [10/12] soc: xilinx: vcu: make the PLL configurable [11/12] soc: xilinx: vcu: remove calculation of PLL configuration [12/12] soc: xilinx: vcu: use bitfields for register definition

Message ID

20201116075532.4019252-4-m.tretter@pengutronix.de (mailing list archive)

State

Not Applicable, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 810722222E
From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org
Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com,
        rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de,
        robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
        Michael Tretter <m.tretter@pengutronix.de>
Date: Mon, 16 Nov 2020 08:55:23 +0100
Message-Id: <20201116075532.4019252-4-m.tretter@pengutronix.de>
In-Reply-To: <20201116075532.4019252-1-m.tretter@pengutronix.de>
References: <20201116075532.4019252-1-m.tretter@pengutronix.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [PATCH 03/12] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu
Precedence: bulk

Series

[01/12] ARM: dts: define indexes for output clocks | expand

Commit Message

Michael Tretter Nov. 16, 2020, 7:55 a.m. UTC

The coreclk field is newer read after being written to xlnx_vcu. Remove
the coreclk field from the xlnx_vcu and use a function local variable
instead.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/soc/xilinx/xlnx_vcu.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
index 14daad4efc58..7da9643820a8 100644
--- a/drivers/soc/xilinx/xlnx_vcu.c
+++ b/drivers/soc/xilinx/xlnx_vcu.c
@@ -73,7 +73,6 @@ 
  * @aclk: axi clock source
  * @logicore_reg_ba: logicore reg base address
  * @vcu_slcr_ba: vcu_slcr Register base address
- * @coreclk: core clock frequency
  */
 struct xvcu_device {
 	struct device *dev;
@@ -81,7 +80,6 @@  struct xvcu_device {
 	struct clk *aclk;
 	struct regmap *logicore_reg_ba;
 	void __iomem *vcu_slcr_ba;
-	u32 coreclk;
 };
 
 static struct regmap_config vcu_settings_regmap_config = {
@@ -358,10 +356,10 @@  static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu)
 		return -EINVAL;
 	}
 
-	xvcu->coreclk = pll_clk / divisor_core;
+	coreclk = pll_clk / divisor_core;
 	mcuclk = pll_clk / divisor_mcu;
 	dev_dbg(xvcu->dev, "Actual Ref clock freq is %uHz\n", refclk);
-	dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk);
+	dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", coreclk);
 	dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk);
 
 	vcu_pll_ctrl &= ~(VCU_PLL_CTRL_FBDIV_MASK << VCU_PLL_CTRL_FBDIV_SHIFT);

[03/12] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu

Commit Message

Patch