| Message ID | 20201125172618.112707-2-zhouyanjie@wanyeetech.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add new clocks for Ingenic SoCs. | expand |
Hi, Le jeu. 26 nov. 2020 à 1:26, 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> a écrit : > Add "jz4780_core1_disable()" for disable the second core of JZ4780, > prepare for later commits. > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Stephen: this patch can be merged independently of the others. Cheers, -Paul > --- > drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/clk/ingenic/jz4780-cgu.c > b/drivers/clk/ingenic/jz4780-cgu.c > index 0268d23..dcca74e 100644 > --- a/drivers/clk/ingenic/jz4780-cgu.c > +++ b/drivers/clk/ingenic/jz4780-cgu.c > @@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw) > return 0; > } > > +static void jz4780_core1_disable(struct clk_hw *hw) > +{ > + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); > + struct ingenic_cgu *cgu = ingenic_clk->cgu; > + unsigned long flags; > + u32 lcr, clkgr1; > + > + spin_lock_irqsave(&cgu->lock, flags); > + > + lcr = readl(cgu->base + CGU_REG_LCR); > + lcr |= LCR_PD_SCPU; > + writel(lcr, cgu->base + CGU_REG_LCR); > + > + clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); > + clkgr1 |= CLKGR1_CORE1; > + writel(clkgr1, cgu->base + CGU_REG_CLKGR1); > + > + spin_unlock_irqrestore(&cgu->lock, flags); > +} > + > static const struct clk_ops jz4780_core1_ops = { > .enable = jz4780_core1_enable, > + .disable = jz4780_core1_disable, > }; > > static const s8 pll_od_encoding[16] = { > -- > 2.7.4 >
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index 0268d23..dcca74e 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw) return 0; } +static void jz4780_core1_disable(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + unsigned long flags; + u32 lcr, clkgr1; + + spin_lock_irqsave(&cgu->lock, flags); + + lcr = readl(cgu->base + CGU_REG_LCR); + lcr |= LCR_PD_SCPU; + writel(lcr, cgu->base + CGU_REG_LCR); + + clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); + clkgr1 |= CLKGR1_CORE1; + writel(clkgr1, cgu->base + CGU_REG_CLKGR1); + + spin_unlock_irqrestore(&cgu->lock, flags); +} + static const struct clk_ops jz4780_core1_ops = { .enable = jz4780_core1_enable, + .disable = jz4780_core1_disable, }; static const s8 pll_od_encoding[16] = {
Add "jz4780_core1_disable()" for disable the second core of JZ4780, prepare for later commits. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)