| Message ID | 20201126221416.3110341-2-niklas.soderlund+renesas@ragnatech.se (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: renesas: r8a779a0: Add clocks to support thermal | expand |
Hi Niklas, On Thu, Nov 26, 2020 at 11:14 PM Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> wrote: > Implement support for the CP clock on V3U. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Thanks for your patch! Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Note that this change was also included in "[PATCH/RFC 3/6] clk: renesas: r8a779a0: Add PFC/GPIO clocks". https://lore.kernel.org/linux-renesas-soc/20201019120614.22149-4-geert+renesas@glider.be/ Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index aa5389b04d74204b..7bf7a98cdb7bb5be 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -139,6 +139,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_MAIN, 2, 1), + DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
Implement support for the CP clock on V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+)