| Message ID | 20201202135409.13683-5-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [1/8] clk: sunxi-ng: h6: Fix clock divider range on some clocks | expand |
于 2020年12月2日 GMT+08:00 下午9:54:05, Andre Przywara <andre.przywara@arm.com> 写到: >The clocks itself are identical to the H6 R-CCU, it's just that the >H616 >has not all of them implemented (or connected). For selective clocks, try to follow the practice of V3(s) driver? > >Signed-off-by: Andre Przywara <andre.przywara@arm.com> >--- > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++- > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- > 2 files changed, 48 insertions(+), 2 deletions(-) > >diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >index 50f8d1bc7046..119d1797f501 100644 >--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >@@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = >{ > &w1_clk.common, > }; > >+static struct ccu_common *sun50i_h616_r_ccu_clks[] = { >+ &r_apb1_clk.common, >+ &r_apb2_clk.common, >+ &r_apb1_twd_clk.common, >+ &r_apb2_i2c_clk.common, >+ &r_apb1_ir_clk.common, >+ &ir_clk.common, >+}; >+ > static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { > .hws = { > [CLK_AR100] = &ar100_clk.common.hw, >@@ -152,7 +161,20 @@ static struct clk_hw_onecell_data >sun50i_h6_r_hw_clks = { > [CLK_IR] = &ir_clk.common.hw, > [CLK_W1] = &w1_clk.common.hw, > }, >- .num = CLK_NUMBER, >+ .num = CLK_NUMBER_H616, >+}; >+ >+static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { >+ .hws = { >+ [CLK_R_AHB] = &r_ahb_clk.hw, >+ [CLK_R_APB1] = &r_apb1_clk.common.hw, >+ [CLK_R_APB2] = &r_apb2_clk.common.hw, >+ [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, >+ [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, >+ [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, >+ [CLK_IR] = &ir_clk.common.hw, >+ }, >+ .num = CLK_NUMBER_H616, > }; > > static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { >@@ -165,6 +187,12 @@ static struct ccu_reset_map >sun50i_h6_r_ccu_resets[] = { > [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, > }; > >+static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { >+ [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, >+ [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, >+ [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, >+}; >+ > static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { > .ccu_clks = sun50i_h6_r_ccu_clks, > .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), >@@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc >sun50i_h6_r_ccu_desc = { > .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), > }; > >+static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { >+ .ccu_clks = sun50i_h616_r_ccu_clks, >+ .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), >+ >+ .hw_clks = &sun50i_h616_r_hw_clks, >+ >+ .resets = sun50i_h616_r_ccu_resets, >+ .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), >+}; >+ > static void __init sunxi_r_ccu_init(struct device_node *node, > const struct sunxi_ccu_desc *desc) > { >@@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct >device_node *node) > } > CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", > sun50i_h6_r_ccu_setup); >+ >+static void __init sun50i_h616_r_ccu_setup(struct device_node *node) >+{ >+ sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); >+} >+CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", >+ sun50i_h616_r_ccu_setup); >diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >index 782117dc0b28..128302696ca1 100644 >--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >@@ -14,6 +14,7 @@ > > #define CLK_R_APB2 3 > >-#define CLK_NUMBER (CLK_W1 + 1) >+#define CLK_NUMBER_H6 (CLK_W1 + 1) >+#define CLK_NUMBER_H616 (CLK_IR + 1) > > #endif /* _CCU_SUN50I_H6_R_H */
Dne sreda, 02. december 2020 ob 14:54:05 CET je Andre Przywara napisal(a): > The clocks itself are identical to the H6 R-CCU, it's just that the H616 > has not all of them implemented (or connected). > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++- > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- > 2 files changed, 48 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ ccu-sun50i-h6-r.c > index 50f8d1bc7046..119d1797f501 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > @@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = { > &w1_clk.common, > }; > > +static struct ccu_common *sun50i_h616_r_ccu_clks[] = { > + &r_apb1_clk.common, > + &r_apb2_clk.common, > + &r_apb1_twd_clk.common, > + &r_apb2_i2c_clk.common, > + &r_apb1_ir_clk.common, > + &ir_clk.common, > +}; > + > static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { > .hws = { > [CLK_AR100] = &ar100_clk.common.hw, > @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { > [CLK_IR] = &ir_clk.common.hw, > [CLK_W1] = &w1_clk.common.hw, > }, > - .num = CLK_NUMBER, > + .num = CLK_NUMBER_H616, Above macro should be CLK_NUMBER_H6. > +}; > + > +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { > + .hws = { > + [CLK_R_AHB] = &r_ahb_clk.hw, > + [CLK_R_APB1] = &r_apb1_clk.common.hw, > + [CLK_R_APB2] = &r_apb2_clk.common.hw, > + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, Do we know if TWD exists? I tested I2C and IR. What is your source for these clocks? Best regards, Jernej > + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, > + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, > + [CLK_IR] = &ir_clk.common.hw, > + }, > + .num = CLK_NUMBER_H616, > }; > > static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { > @@ -165,6 +187,12 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { > [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, > }; > > +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { > + [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, > + [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, > + [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, > +}; > + > static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { > .ccu_clks = sun50i_h6_r_ccu_clks, > .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), > @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { > .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), > }; > > +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { > + .ccu_clks = sun50i_h616_r_ccu_clks, > + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), > + > + .hw_clks = &sun50i_h616_r_hw_clks, > + > + .resets = sun50i_h616_r_ccu_resets, > + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), > +}; > + > static void __init sunxi_r_ccu_init(struct device_node *node, > const struct sunxi_ccu_desc *desc) > { > @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct device_node *node) > } > CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", > sun50i_h6_r_ccu_setup); > + > +static void __init sun50i_h616_r_ccu_setup(struct device_node *node) > +{ > + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); > +} > +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", > + sun50i_h616_r_ccu_setup); > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ ccu-sun50i-h6-r.h > index 782117dc0b28..128302696ca1 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > @@ -14,6 +14,7 @@ > > #define CLK_R_APB2 3 > > -#define CLK_NUMBER (CLK_W1 + 1) > +#define CLK_NUMBER_H6 (CLK_W1 + 1) > +#define CLK_NUMBER_H616 (CLK_IR + 1) > > #endif /* _CCU_SUN50I_H6_R_H */ > -- > 2.17.5 > >
On 12/2/20 12:20 PM, Jernej Škrabec wrote: >> +}; >> + >> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { >> + .hws = { >> + [CLK_R_AHB] = &r_ahb_clk.hw, >> + [CLK_R_APB1] = &r_apb1_clk.common.hw, >> + [CLK_R_APB2] = &r_apb2_clk.common.hw, >> + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, > > Do we know if TWD exists? I tested I2C and IR. What is your source for these > clocks? Looking at https://github.com/orangepi-xunlong/linux-orangepi and comparing drivers/clk/sunxi/clk-sun50iw[69].h, I see: /* PRCM Register List */ #define CPUS_CFG 0x0000 #define CPUS_APBS1_CFG 0x000C #define CPUS_APBS2_CFG 0x0010 -#define CPUS_TIMER_GATE 0x011C #define CPUS_TWDOG_GATE 0x012C -#define CPUS_PWM_GATE 0x013C -#define CPUS_UART_GATE 0x018C #define CPUS_TWI_GATE 0x019C #define CPUS_RSB_GATE 0x01BC #define CPUS_CIR_CFG 0x01C0 #define CPUS_CIR_GATE 0x01CC #define CPUS_OWC_CFG 0x01E0 #define CPUS_OWC_GATE 0x01EC #define CPUS_RTC_GATE 0x020C #define CPUS_CLK_MAX_REG 0x020C which suggests that TWD is still there, along with OWC/W1 and an undocumented RSB controller like the one in H6. Jernej, can you check RSB? It should be PL0/PL1 function 2 and MMIO base 0x7083000. Cheers, Samuel
On 02/12/2020 18:20, Jernej Škrabec wrote: Hi, > Dne sreda, 02. december 2020 ob 14:54:05 CET je Andre Przywara napisal(a): >> The clocks itself are identical to the H6 R-CCU, it's just that the H616 >> has not all of them implemented (or connected). >> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >> --- >> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++- >> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- >> 2 files changed, 48 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >> index 50f8d1bc7046..119d1797f501 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >> @@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = { >> &w1_clk.common, >> }; >> >> +static struct ccu_common *sun50i_h616_r_ccu_clks[] = { >> + &r_apb1_clk.common, >> + &r_apb2_clk.common, >> + &r_apb1_twd_clk.common, >> + &r_apb2_i2c_clk.common, >> + &r_apb1_ir_clk.common, >> + &ir_clk.common, >> +}; >> + >> static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { >> .hws = { >> [CLK_AR100] = &ar100_clk.common.hw, >> @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { >> [CLK_IR] = &ir_clk.common.hw, >> [CLK_W1] = &w1_clk.common.hw, >> }, >> - .num = CLK_NUMBER, >> + .num = CLK_NUMBER_H616, > > Above macro should be CLK_NUMBER_H6. Ouch, well spotted! >> +}; >> + >> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { >> + .hws = { >> + [CLK_R_AHB] = &r_ahb_clk.hw, >> + [CLK_R_APB1] = &r_apb1_clk.common.hw, >> + [CLK_R_APB2] = &r_apb2_clk.common.hw, >> + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, > > Do we know if TWD exists? I tested I2C and IR. What is your source for these > clocks? I poked around in this area, writing all Fs into those clock registers and checked which stuck. There are actually even more clocks still around there, though not all of the H6 (no PWM, for instance). For TWD: it's mentioned in the manual, the clock register is there and can be written to. The normal watchdog registers do not appear to work at 0x7020800 (they are RAZ/WI), but there is a counter at 0x7020820, which increments as long as those TWD clock gates are open. It stops when the clock bits are cleared. So that tells me that this clock is there and is working. I didn't have time yet to check the other (former) peripherals from that area. Cheers, Andre > > Best regards, > Jernej > >> + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, >> + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, >> + [CLK_IR] = &ir_clk.common.hw, >> + }, >> + .num = CLK_NUMBER_H616, >> }; >> >> static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { >> @@ -165,6 +187,12 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { >> [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, >> }; >> >> +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { >> + [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, >> + [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, >> + [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, >> +}; >> + >> static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { >> .ccu_clks = sun50i_h6_r_ccu_clks, >> .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), >> @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { >> .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), >> }; >> >> +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { >> + .ccu_clks = sun50i_h616_r_ccu_clks, >> + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), >> + >> + .hw_clks = &sun50i_h616_r_hw_clks, >> + >> + .resets = sun50i_h616_r_ccu_resets, >> + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), >> +}; >> + >> static void __init sunxi_r_ccu_init(struct device_node *node, >> const struct sunxi_ccu_desc *desc) >> { >> @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct device_node *node) >> } >> CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", >> sun50i_h6_r_ccu_setup); >> + >> +static void __init sun50i_h616_r_ccu_setup(struct device_node *node) >> +{ >> + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); >> +} >> +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", >> + sun50i_h616_r_ccu_setup); >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >> index 782117dc0b28..128302696ca1 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >> @@ -14,6 +14,7 @@ >> >> #define CLK_R_APB2 3 >> >> -#define CLK_NUMBER (CLK_W1 + 1) >> +#define CLK_NUMBER_H6 (CLK_W1 + 1) >> +#define CLK_NUMBER_H616 (CLK_IR + 1) >> >> #endif /* _CCU_SUN50I_H6_R_H */ >> -- >> 2.17.5 >> >>
On 02/12/2020 14:31, Icenowy Zheng wrote: Hi, > 于 2020年12月2日 GMT+08:00 下午9:54:05, Andre Przywara <andre.przywara@arm.com> 写到: >> The clocks itself are identical to the H6 R-CCU, it's just that the >> H616 >> has not all of them implemented (or connected). > > For selective clocks, try to follow the practice of V3(s) driver? Not sure what you mean, isn't that what I do? Having a separate sunxi_ccu_desc for each SoC and referencing separate structs? At least that's what I see in ccu-sun8i-v3s.c. What am I missing? Cheers, Andre >> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >> --- >> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++- >> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- >> 2 files changed, 48 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >> index 50f8d1bc7046..119d1797f501 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >> @@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = >> { >> &w1_clk.common, >> }; >> >> +static struct ccu_common *sun50i_h616_r_ccu_clks[] = { >> + &r_apb1_clk.common, >> + &r_apb2_clk.common, >> + &r_apb1_twd_clk.common, >> + &r_apb2_i2c_clk.common, >> + &r_apb1_ir_clk.common, >> + &ir_clk.common, >> +}; >> + >> static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { >> .hws = { >> [CLK_AR100] = &ar100_clk.common.hw, >> @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data >> sun50i_h6_r_hw_clks = { >> [CLK_IR] = &ir_clk.common.hw, >> [CLK_W1] = &w1_clk.common.hw, >> }, >> - .num = CLK_NUMBER, >> + .num = CLK_NUMBER_H616, >> +}; >> + >> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { >> + .hws = { >> + [CLK_R_AHB] = &r_ahb_clk.hw, >> + [CLK_R_APB1] = &r_apb1_clk.common.hw, >> + [CLK_R_APB2] = &r_apb2_clk.common.hw, >> + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, >> + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, >> + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, >> + [CLK_IR] = &ir_clk.common.hw, >> + }, >> + .num = CLK_NUMBER_H616, >> }; >> >> static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { >> @@ -165,6 +187,12 @@ static struct ccu_reset_map >> sun50i_h6_r_ccu_resets[] = { >> [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, >> }; >> >> +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { >> + [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, >> + [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, >> + [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, >> +}; >> + >> static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { >> .ccu_clks = sun50i_h6_r_ccu_clks, >> .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), >> @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc >> sun50i_h6_r_ccu_desc = { >> .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), >> }; >> >> +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { >> + .ccu_clks = sun50i_h616_r_ccu_clks, >> + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), >> + >> + .hw_clks = &sun50i_h616_r_hw_clks, >> + >> + .resets = sun50i_h616_r_ccu_resets, >> + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), >> +}; >> + >> static void __init sunxi_r_ccu_init(struct device_node *node, >> const struct sunxi_ccu_desc *desc) >> { >> @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct >> device_node *node) >> } >> CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", >> sun50i_h6_r_ccu_setup); >> + >> +static void __init sun50i_h616_r_ccu_setup(struct device_node *node) >> +{ >> + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); >> +} >> +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", >> + sun50i_h616_r_ccu_setup); >> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >> index 782117dc0b28..128302696ca1 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >> @@ -14,6 +14,7 @@ >> >> #define CLK_R_APB2 3 >> >> -#define CLK_NUMBER (CLK_W1 + 1) >> +#define CLK_NUMBER_H6 (CLK_W1 + 1) >> +#define CLK_NUMBER_H616 (CLK_IR + 1) >> >> #endif /* _CCU_SUN50I_H6_R_H */
于 2020年12月3日 GMT+08:00 下午7:07:02, "André Przywara" <andre.przywara@arm.com> 写到: >On 02/12/2020 14:31, Icenowy Zheng wrote: > >Hi, > >> 于 2020年12月2日 GMT+08:00 下午9:54:05, Andre Przywara ><andre.przywara@arm.com> 写到: >>> The clocks itself are identical to the H6 R-CCU, it's just that the >>> H616 >>> has not all of them implemented (or connected). >> >> For selective clocks, try to follow the practice of V3(s) driver? > >Not sure what you mean, isn't that what I do? Having a separate >sunxi_ccu_desc for each SoC and referencing separate structs? At least >that's what I see in ccu-sun8i-v3s.c. > >What am I missing? Sorry, I misred it. Ignore my disturbance. > >Cheers, >Andre > >>> >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com> >>> --- >>> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 >+++++++++++++++++++++++++- >>> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- >>> 2 files changed, 48 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >>> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >>> index 50f8d1bc7046..119d1797f501 100644 >>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c >>> @@ -136,6 +136,15 @@ static struct ccu_common >*sun50i_h6_r_ccu_clks[] = >>> { >>> &w1_clk.common, >>> }; >>> >>> +static struct ccu_common *sun50i_h616_r_ccu_clks[] = { >>> + &r_apb1_clk.common, >>> + &r_apb2_clk.common, >>> + &r_apb1_twd_clk.common, >>> + &r_apb2_i2c_clk.common, >>> + &r_apb1_ir_clk.common, >>> + &ir_clk.common, >>> +}; >>> + >>> static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { >>> .hws = { >>> [CLK_AR100] = &ar100_clk.common.hw, >>> @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data >>> sun50i_h6_r_hw_clks = { >>> [CLK_IR] = &ir_clk.common.hw, >>> [CLK_W1] = &w1_clk.common.hw, >>> }, >>> - .num = CLK_NUMBER, >>> + .num = CLK_NUMBER_H616, >>> +}; >>> + >>> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { >>> + .hws = { >>> + [CLK_R_AHB] = &r_ahb_clk.hw, >>> + [CLK_R_APB1] = &r_apb1_clk.common.hw, >>> + [CLK_R_APB2] = &r_apb2_clk.common.hw, >>> + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, >>> + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, >>> + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, >>> + [CLK_IR] = &ir_clk.common.hw, >>> + }, >>> + .num = CLK_NUMBER_H616, >>> }; >>> >>> static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { >>> @@ -165,6 +187,12 @@ static struct ccu_reset_map >>> sun50i_h6_r_ccu_resets[] = { >>> [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, >>> }; >>> >>> +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { >>> + [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, >>> + [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, >>> + [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, >>> +}; >>> + >>> static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { >>> .ccu_clks = sun50i_h6_r_ccu_clks, >>> .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), >>> @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc >>> sun50i_h6_r_ccu_desc = { >>> .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), >>> }; >>> >>> +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { >>> + .ccu_clks = sun50i_h616_r_ccu_clks, >>> + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), >>> + >>> + .hw_clks = &sun50i_h616_r_hw_clks, >>> + >>> + .resets = sun50i_h616_r_ccu_resets, >>> + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), >>> +}; >>> + >>> static void __init sunxi_r_ccu_init(struct device_node *node, >>> const struct sunxi_ccu_desc *desc) >>> { >>> @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct >>> device_node *node) >>> } >>> CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", >>> sun50i_h6_r_ccu_setup); >>> + >>> +static void __init sun50i_h616_r_ccu_setup(struct device_node >*node) >>> +{ >>> + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); >>> +} >>> +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", >>> + sun50i_h616_r_ccu_setup); >>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >>> b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >>> index 782117dc0b28..128302696ca1 100644 >>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h >>> @@ -14,6 +14,7 @@ >>> >>> #define CLK_R_APB2 3 >>> >>> -#define CLK_NUMBER (CLK_W1 + 1) >>> +#define CLK_NUMBER_H6 (CLK_W1 + 1) >>> +#define CLK_NUMBER_H616 (CLK_IR + 1) >>> >>> #endif /* _CCU_SUN50I_H6_R_H */
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c index 50f8d1bc7046..119d1797f501 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -136,6 +136,15 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = { &w1_clk.common, }; +static struct ccu_common *sun50i_h616_r_ccu_clks[] = { + &r_apb1_clk.common, + &r_apb2_clk.common, + &r_apb1_twd_clk.common, + &r_apb2_i2c_clk.common, + &r_apb1_ir_clk.common, + &ir_clk.common, +}; + static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { .hws = { [CLK_AR100] = &ar100_clk.common.hw, @@ -152,7 +161,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { [CLK_IR] = &ir_clk.common.hw, [CLK_W1] = &w1_clk.common.hw, }, - .num = CLK_NUMBER, + .num = CLK_NUMBER_H616, +}; + +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { + .hws = { + [CLK_R_AHB] = &r_ahb_clk.hw, + [CLK_R_APB1] = &r_apb1_clk.common.hw, + [CLK_R_APB2] = &r_apb2_clk.common.hw, + [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, + [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, + [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER_H616, }; static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { @@ -165,6 +187,12 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { [RST_R_APB1_W1] = { 0x1ec, BIT(16) }, }; +static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = { + [RST_R_APB1_TWD] = { 0x12c, BIT(16) }, + [RST_R_APB2_I2C] = { 0x19c, BIT(16) }, + [RST_R_APB1_IR] = { 0x1cc, BIT(16) }, +}; + static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { .ccu_clks = sun50i_h6_r_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks), @@ -175,6 +203,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = { .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets), }; +static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = { + .ccu_clks = sun50i_h616_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks), + + .hw_clks = &sun50i_h616_r_hw_clks, + + .resets = sun50i_h616_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets), +}; + static void __init sunxi_r_ccu_init(struct device_node *node, const struct sunxi_ccu_desc *desc) { @@ -195,3 +233,10 @@ static void __init sun50i_h6_r_ccu_setup(struct device_node *node) } CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu", sun50i_h6_r_ccu_setup); + +static void __init sun50i_h616_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc); +} +CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu", + sun50i_h616_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h index 782117dc0b28..128302696ca1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h @@ -14,6 +14,7 @@ #define CLK_R_APB2 3 -#define CLK_NUMBER (CLK_W1 + 1) +#define CLK_NUMBER_H6 (CLK_W1 + 1) +#define CLK_NUMBER_H616 (CLK_IR + 1) #endif /* _CCU_SUN50I_H6_R_H */
The clocks itself are identical to the H6 R-CCU, it's just that the H616 has not all of them implemented (or connected). Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 47 +++++++++++++++++++++++++- drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 3 +- 2 files changed, 48 insertions(+), 2 deletions(-)