| Message ID | 20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | [1/2] clk: qcom: gcc-sc7180: Use floor ops for sdcc clks | expand |
On Thu 10 Dec 12:22 CST 2020, Douglas Anderson wrote: > I would repeat the same commit message that was in commit 5e4b7e82d497 > ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems > silly to do so when you could just go read that commit. > > NOTE: this is actually extra terrible because we're missing the 50 MHz > rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add > 50 MHz clock rate for SDC2")). That means then when you run an older > SD card it'll try to clock it at 100 MHz when it's only specced to run > at 50 MHz max. As you can probably guess that doesn't work super > well. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") > --- > Taniya: can you please update whatever process is used to generate > these clock files to use floor for SD card clocks. I hope you can > also scour through these files looking for similar problems on other > SoCs and submit patches for them. > > drivers/clk/qcom/gcc-sc7180.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c > index 68d8f7aaf64e..b080739ab0c3 100644 > --- a/drivers/clk/qcom/gcc-sc7180.c > +++ b/drivers/clk/qcom/gcc-sc7180.c > @@ -642,7 +642,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { > .name = "gcc_sdcc1_ice_core_clk_src", > .parent_data = gcc_parent_data_0, > .num_parents = 4, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_floor_ops, > }, > }; > > @@ -666,7 +666,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { > .name = "gcc_sdcc2_apps_clk_src", > .parent_data = gcc_parent_data_5, > .num_parents = 5, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_floor_ops, > }, > }; > > -- > 2.29.2.576.ga3fc446d84-goog >
Quoting Douglas Anderson (2020-12-10 10:22:38) > I would repeat the same commit message that was in commit 5e4b7e82d497 > ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems > silly to do so when you could just go read that commit. > > NOTE: this is actually extra terrible because we're missing the 50 MHz > rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add > 50 MHz clock rate for SDC2")). That means then when you run an older > SD card it'll try to clock it at 100 MHz when it's only specced to run > at 50 MHz max. As you can probably guess that doesn't work super > well. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") > --- > Taniya: can you please update whatever process is used to generate > these clock files to use floor for SD card clocks. I hope you can > also scour through these files looking for similar problems on other > SoCs and submit patches for them. Any chance the consumer of this clk can call clk_round_rate() and WARN() if the rate is not anywhere near what it wants it to be? I fear that this problem will just keep coming up otherwise.
Quoting Douglas Anderson (2020-12-10 10:22:38) > I would repeat the same commit message that was in commit 5e4b7e82d497 > ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems > silly to do so when you could just go read that commit. > > NOTE: this is actually extra terrible because we're missing the 50 MHz > rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add > 50 MHz clock rate for SDC2")). That means then when you run an older > SD card it'll try to clock it at 100 MHz when it's only specced to run > at 50 MHz max. As you can probably guess that doesn't work super > well. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") > --- Applied to clk-next
Hi, On Thu, Dec 10, 2020 at 12:27 PM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Douglas Anderson (2020-12-10 10:22:38) > > I would repeat the same commit message that was in commit 5e4b7e82d497 > > ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems > > silly to do so when you could just go read that commit. > > > > NOTE: this is actually extra terrible because we're missing the 50 MHz > > rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add > > 50 MHz clock rate for SDC2")). That means then when you run an older > > SD card it'll try to clock it at 100 MHz when it's only specced to run > > at 50 MHz max. As you can probably guess that doesn't work super > > well. > > > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > > Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") > > --- > > Taniya: can you please update whatever process is used to generate > > these clock files to use floor for SD card clocks. I hope you can > > also scour through these files looking for similar problems on other > > SoCs and submit patches for them. > > Any chance the consumer of this clk can call clk_round_rate() and WARN() > if the rate is not anywhere near what it wants it to be? I fear that > this problem will just keep coming up otherwise. Good idea. Posted ("[PATCH] mmc: sdhci-msm: Warn about overclocking SD/MMC") [1]. I just checked for the clock being higher, not lower and I did a normal print rather than a WARN splat. Interestingly this shows that we were also overclocking the eMMC during probe (though we end up at a proper rate in the end). I saw these transitory errors during boot: [ 6.287870] mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz [ 6.295811] mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz [ 6.312573] mmc0: Card appears overclocked; req 104000000 Hz, actual 192000000 Hz [1] https://lore.kernel.org/r/20201210125709.1.Iec3430c7d3c2a29262695edef7b82a14aaa567e5@changeid -Doug
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index 68d8f7aaf64e..b080739ab0c3 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -642,7 +642,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = 4, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; @@ -666,7 +666,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_5, .num_parents = 5, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, };
I would repeat the same commit message that was in commit 5e4b7e82d497 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems silly to do so when you could just go read that commit. NOTE: this is actually extra terrible because we're missing the 50 MHz rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2")). That means then when you run an older SD card it'll try to clock it at 100 MHz when it's only specced to run at 50 MHz max. As you can probably guess that doesn't work super well. Signed-off-by: Douglas Anderson <dianders@chromium.org> Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") --- Taniya: can you please update whatever process is used to generate these clock files to use floor for SD card clocks. I hope you can also scour through these files looking for similar problems on other SoCs and submit patches for them. drivers/clk/qcom/gcc-sc7180.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)