Message ID | 20201216151931.851547-3-kieran.bingham+renesas@ideasonboard.com (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | clk: renesas: r8a779a0: Add FCP and VSP support | expand |
On Wed, Dec 16, 2020 at 4:19 PM Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> wrote: > Add clocks for the VSPD modules on the V3U. > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> In BSP we trust (for the parent clocks)... Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.12. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 8160f41191b2..2ce31508db73 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -190,6 +190,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1), DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1), DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), + DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), + DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), }; static spinlock_t cpg_lock;
Add clocks for the VSPD modules on the V3U. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+)