[v2,13/15] soc: xilinx: vcu: fix repeated word the in comment

From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com,
        rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de,
        mturquette@baylibre.com, sboyd@kernel.org
Subject: [PATCH v2 13/15] soc: xilinx: vcu: fix repeated word the in comment
Date: Mon, 21 Dec 2020 16:06:32 +0100
Message-Id: <20201221150634.755673-14-m.tretter@pengutronix.de>
In-Reply-To: <20201221150634.755673-1-m.tretter@pengutronix.de>
References: <20201221150634.755673-1-m.tretter@pengutronix.de>
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Message ID	20201221150634.755673-14-m.tretter@pengutronix.de (mailing list archive)
State	Superseded, archived
Headers	show Return-Path: <linux-clk-owner@kernel.org> From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com, rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org Subject: [PATCH v2 13/15] soc: xilinx: vcu: fix repeated word the in comment Date: Mon, 21 Dec 2020 16:06:32 +0100 Message-Id: <20201221150634.755673-14-m.tretter@pengutronix.de> In-Reply-To: <20201221150634.755673-1-m.tretter@pengutronix.de> References: <20201221150634.755673-1-m.tretter@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	soc: xilinx: vcu: Convert driver to clock provider \| expand [v2,00/15] soc: xilinx: vcu: Convert driver to clock provider [v2,01/15] ARM: dts: vcu: define indexes for output clocks [v2,02/15] clk: divider: fix initialization with parent_hw [v2,03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu [v2,04/15] soc: xilinx: vcu: add helper to wait for PLL locked [v2,05/15] soc: xilinx: vcu: add helpers for configuring PLL [v2,06/15] soc: xilinx: vcu: implement PLL disable [v2,07/15] soc: xilinx: vcu: register PLL as fixed rate clock [v2,08/15] soc: xilinx: vcu: implement clock provider for output clocks [v2,09/15] soc: xilinx: vcu: make pll post divider explicit [v2,10/15] soc: xilinx: vcu: make the PLL configurable [v2,11/15] soc: xilinx: vcu: remove calculation of PLL configuration [v2,12/15] soc: xilinx: vcu: use bitfields for register definition [v2,13/15] soc: xilinx: vcu: fix repeated word the in comment [v2,14/15] soc: xilinx: vcu: fix alignment to open parenthesis [v2,15/15] clk: xilinx: move xlnx_vcu clock driver from soc

[v2,13/15] soc: xilinx: vcu: fix repeated word the in comment

Commit Message

Patch