[v2,02/15] clk: divider: fix initialization with parent_hw

Message ID	20201221150634.755673-3-m.tretter@pengutronix.de (mailing list archive)
State	Superseded, archived
Headers	show Return-Path: <linux-clk-owner@kernel.org> From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com, rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org Subject: [PATCH v2 02/15] clk: divider: fix initialization with parent_hw Date: Mon, 21 Dec 2020 16:06:21 +0100 Message-Id: <20201221150634.755673-3-m.tretter@pengutronix.de> In-Reply-To: <20201221150634.755673-1-m.tretter@pengutronix.de> References: <20201221150634.755673-1-m.tretter@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	soc: xilinx: vcu: Convert driver to clock provider \| expand [v2,00/15] soc: xilinx: vcu: Convert driver to clock provider [v2,01/15] ARM: dts: vcu: define indexes for output clocks [v2,02/15] clk: divider: fix initialization with parent_hw [v2,03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu [v2,04/15] soc: xilinx: vcu: add helper to wait for PLL locked [v2,05/15] soc: xilinx: vcu: add helpers for configuring PLL [v2,06/15] soc: xilinx: vcu: implement PLL disable [v2,07/15] soc: xilinx: vcu: register PLL as fixed rate clock [v2,08/15] soc: xilinx: vcu: implement clock provider for output clocks [v2,09/15] soc: xilinx: vcu: make pll post divider explicit [v2,10/15] soc: xilinx: vcu: make the PLL configurable [v2,11/15] soc: xilinx: vcu: remove calculation of PLL configuration [v2,12/15] soc: xilinx: vcu: use bitfields for register definition [v2,13/15] soc: xilinx: vcu: fix repeated word the in comment [v2,14/15] soc: xilinx: vcu: fix alignment to open parenthesis [v2,15/15] clk: xilinx: move xlnx_vcu clock driver from soc

Message ID

20201221150634.755673-3-m.tretter@pengutronix.de (mailing list archive)

State

Superseded, archived

Headers

From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com,
        rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de,
        mturquette@baylibre.com, sboyd@kernel.org
Subject: [PATCH v2 02/15] clk: divider: fix initialization with parent_hw
Date: Mon, 21 Dec 2020 16:06:21 +0100
Message-Id: <20201221150634.755673-3-m.tretter@pengutronix.de>
In-Reply-To: <20201221150634.755673-1-m.tretter@pengutronix.de>
References: <20201221150634.755673-1-m.tretter@pengutronix.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

soc: xilinx: vcu: Convert driver to clock provider | expand

Commit Message

Michael Tretter Dec. 21, 2020, 3:06 p.m. UTC

If a driver registers a divider clock with a parent_hw instead of the
parent_name, the parent_hw is ignored and the clock does not have a
parent.

Fix this by initializing the parents the same way they are initialized
for clock gates.

Fixes: ff258817137a ("clk: divider: Add support for specifying parents via DT/pointers")
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
Changelog:

v2:
- Add fixes tag
---
 drivers/clk/clk-divider.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8de12cb0c43d..f32157cb4013 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -493,8 +493,13 @@  struct clk_hw *__clk_hw_register_divider(struct device *dev,
 	else
 		init.ops = &clk_divider_ops;
 	init.flags = flags;
-	init.parent_names = (parent_name ? &parent_name: NULL);
-	init.num_parents = (parent_name ? 1 : 0);
+	init.parent_names = parent_name ? &parent_name : NULL;
+	init.parent_hws = parent_hw ? &parent_hw : NULL;
+	init.parent_data = parent_data;
+	if (parent_name || parent_hw || parent_data)
+		init.num_parents = 1;
+	else
+		init.num_parents = 0;
 
 	/* struct clk_divider assignments */
 	div->reg = reg;

[v2,02/15] clk: divider: fix initialization with parent_hw

Commit Message

Patch