[v2,06/15] soc: xilinx: vcu: implement PLL disable

Message ID	20201221150634.755673-7-m.tretter@pengutronix.de (mailing list archive)
State	Superseded, archived
Headers	show Return-Path: <linux-clk-owner@kernel.org> From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com, rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org Subject: [PATCH v2 06/15] soc: xilinx: vcu: implement PLL disable Date: Mon, 21 Dec 2020 16:06:25 +0100 Message-Id: <20201221150634.755673-7-m.tretter@pengutronix.de> In-Reply-To: <20201221150634.755673-1-m.tretter@pengutronix.de> References: <20201221150634.755673-1-m.tretter@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	soc: xilinx: vcu: Convert driver to clock provider \| expand [v2,00/15] soc: xilinx: vcu: Convert driver to clock provider [v2,01/15] ARM: dts: vcu: define indexes for output clocks [v2,02/15] clk: divider: fix initialization with parent_hw [v2,03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu [v2,04/15] soc: xilinx: vcu: add helper to wait for PLL locked [v2,05/15] soc: xilinx: vcu: add helpers for configuring PLL [v2,06/15] soc: xilinx: vcu: implement PLL disable [v2,07/15] soc: xilinx: vcu: register PLL as fixed rate clock [v2,08/15] soc: xilinx: vcu: implement clock provider for output clocks [v2,09/15] soc: xilinx: vcu: make pll post divider explicit [v2,10/15] soc: xilinx: vcu: make the PLL configurable [v2,11/15] soc: xilinx: vcu: remove calculation of PLL configuration [v2,12/15] soc: xilinx: vcu: use bitfields for register definition [v2,13/15] soc: xilinx: vcu: fix repeated word the in comment [v2,14/15] soc: xilinx: vcu: fix alignment to open parenthesis [v2,15/15] clk: xilinx: move xlnx_vcu clock driver from soc

Message ID

20201221150634.755673-7-m.tretter@pengutronix.de (mailing list archive)

State

Superseded, archived

Headers

From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com,
        rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de,
        mturquette@baylibre.com, sboyd@kernel.org
Subject: [PATCH v2 06/15] soc: xilinx: vcu: implement PLL disable
Date: Mon, 21 Dec 2020 16:06:25 +0100
Message-Id: <20201221150634.755673-7-m.tretter@pengutronix.de>
In-Reply-To: <20201221150634.755673-1-m.tretter@pengutronix.de>
References: <20201221150634.755673-1-m.tretter@pengutronix.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

soc: xilinx: vcu: Convert driver to clock provider | expand

Commit Message

Michael Tretter Dec. 21, 2020, 3:06 p.m. UTC

The disabling of the PLL is not fully implemented, because according to
the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to
be set to bring the PLL into reset.

Set the bits to disable the PLL.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
Changelog:

v2: none
---
 drivers/soc/xilinx/xlnx_vcu.c | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
index ff66551a5966..34f3299afc0d 100644
--- a/drivers/soc/xilinx/xlnx_vcu.c
+++ b/drivers/soc/xilinx/xlnx_vcu.c
@@ -329,6 +329,10 @@  static int xvcu_pll_enable(struct xvcu_device *xvcu)
 		return ret;
 	}
 
+	xvcu_write_field_reg(base, VCU_PLL_CTRL,
+			     1, VCU_PLL_CTRL_BYPASS_MASK,
+			     VCU_PLL_CTRL_BYPASS_SHIFT);
+
 	vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
 	vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
 			  VCU_PLL_CTRL_POR_IN_SHIFT);
@@ -340,15 +344,9 @@  static int xvcu_pll_enable(struct xvcu_device *xvcu)
 			 VCU_PLL_CTRL_PWR_POR_SHIFT;
 	xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
 
-	xvcu_write_field_reg(base, VCU_PLL_CTRL,
-			     1, VCU_PLL_CTRL_BYPASS_MASK,
-			     VCU_PLL_CTRL_BYPASS_SHIFT);
-	xvcu_write_field_reg(base, VCU_PLL_CTRL,
-			     1, VCU_PLL_CTRL_RESET_MASK,
-			     VCU_PLL_CTRL_RESET_SHIFT);
-	xvcu_write_field_reg(base, VCU_PLL_CTRL,
-			     0, VCU_PLL_CTRL_RESET_MASK,
-			     VCU_PLL_CTRL_RESET_SHIFT);
+	vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+	vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+	xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
 
 	ret = xvcu_pll_wait_for_lock(xvcu);
 	if (ret) {
@@ -368,6 +366,18 @@  static int xvcu_pll_enable(struct xvcu_device *xvcu)
 
 static void xvcu_pll_disable(struct xvcu_device *xvcu)
 {
+	void __iomem *base = xvcu->vcu_slcr_ba;
+	u32 vcu_pll_ctrl;
+
+	vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
+	vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK << VCU_PLL_CTRL_POR_IN_SHIFT);
+	vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_POR_IN_MASK) << VCU_PLL_CTRL_POR_IN_SHIFT;
+	vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK << VCU_PLL_CTRL_PWR_POR_SHIFT);
+	vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_PWR_POR_MASK) << VCU_PLL_CTRL_PWR_POR_SHIFT;
+	vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
+	vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
+	xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
+
 	clk_disable_unprepare(xvcu->pll_ref);
 }

[v2,06/15] soc: xilinx: vcu: implement PLL disable

Commit Message

Patch