diff mbox series

[2/5] clk: renesas: r8a779a0: add clocks for RAVB

Message ID 20201227130407.10991-3-wsa+renesas@sang-engineering.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series v3u: add support for RAVB | expand

Commit Message

Wolfram Sang Dec. 27, 2020, 1:04 p.m. UTC 
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Geert Uytterhoeven Jan. 5, 2021, 3:21 p.m. UTC | #1 
Hi Wolfram,

On Sun, Dec 27, 2020 at 2:04 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> @@ -148,6 +148,12 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
>  };
>
>  static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> +       DEF_MOD("avb0",         211,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb1",         212,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb2",         213,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb3",         214,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb4",         215,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb5",         216,    R8A779A0_CLK_S3D1),

For all other SoCs, we used the HP clock (S3D2 on R-Car V3U) instead
of the ZS clock as the parent clock of the EtherAVB module clocks.
Hence I think we should be consequent and use S3D2 here.

>         DEF_MOD("csi40",        331,    R8A779A0_CLK_CSI0),
>         DEF_MOD("csi41",        400,    R8A779A0_CLK_CSI0),
>         DEF_MOD("csi42",        401,    R8A779A0_CLK_CSI0),

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 04514140e615..5be70a6a7904 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -148,6 +148,12 @@  static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+	DEF_MOD("avb0",		211,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb1",		212,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb2",		213,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb3",		214,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb4",		215,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb5",		216,	R8A779A0_CLK_S3D1),
 	DEF_MOD("csi40",	331,	R8A779A0_CLK_CSI0),
 	DEF_MOD("csi41",	400,	R8A779A0_CLK_CSI0),
 	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),