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[2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c4sm99916521wrw.72.2021.01.04.05.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 05:29:14 -0800 (PST) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 3/5] clk: meson: meson8b: add the video clock divider tables Date: Mon, 4 Jan 2021 14:28:04 +0100 Message-Id: <20210104132806.720558-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> References: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add all known clock dividers from Amlogic's 3.10 vendor kernel. If not stated otherwise the values given in the tables are the only ones used by the 3.10 vendor kernel even if the hardware is capable of other dividers as well: - vid_pll_pre_div can divide by 5 or 6 and if u-boot did not initialize this clock then it divides by 1 by default (only 5 and 6 are used at runtime by the vendor kernel though) - vid_pll_post_div is either 1 or 2 - vid_pll_final_div is either 1, 2 or 4 Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 16ab595ab1a4..1ae771bac4a5 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1084,11 +1084,19 @@ static struct clk_regmap meson8b_vid_pll_in_en = { }, }; +static const struct clk_div_table vid_pll_pre_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 4, .div = 5 }, + { .val = 5, .div = 6 }, + { /* sentinel */ } +}; + static struct clk_regmap meson8b_vid_pll_pre_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_VID_DIVIDER_CNTL, .shift = 4, .width = 3, + .table = vid_pll_pre_div_table, }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_pre_div", @@ -1101,11 +1109,18 @@ static struct clk_regmap meson8b_vid_pll_pre_div = { }, }; +static const struct clk_div_table vid_pll_post_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { /* sentinel */ } +}; + static struct clk_regmap meson8b_vid_pll_post_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_VID_DIVIDER_CNTL, .shift = 12, .width = 3, + .table = vid_pll_post_div_table, }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_post_div", @@ -1137,11 +1152,19 @@ static struct clk_regmap meson8b_vid_pll = { }, }; +static const struct clk_div_table meson8b_vid_pll_final_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 3, .div = 4 }, + { /* sentinel */ } +}; + static struct clk_regmap meson8b_vid_pll_final_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_VID_CLK_DIV, .shift = 0, .width = 8, + .table = meson8b_vid_pll_final_div_table, }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_final_div",