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[2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c4sm99916521wrw.72.2021.01.04.05.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 05:29:15 -0800 (PST) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 4/5] clk: meson: meson8b: add the HDMI PLL M/N parameters Date: Mon, 4 Jan 2021 14:28:05 +0100 Message-Id: <20210104132806.720558-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> References: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The 3.10 vendor kernel uses only specific HDMI PLL M/N parameter combinations. The PLL won't lock for values smaller than 50 if the internal doubling (which is yet unknown how to use it) is disabled. However, when this doubling is enabled then the values smaller than 50 will lock just fine. The only restriction for values greater than 50 is that the resulting frequency must not exceed the 3.0GHz limit. These values are taken from the endlessm 3.10 kernel which includes some additional M/N combinations for some VESA and 75Hz display modes. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 1ae771bac4a5..8061c11389a9 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -118,6 +118,28 @@ static struct clk_regmap meson8b_fixed_pll = { }, }; +static const struct pll_params_table hdmi_pll_params_table[] = { + PLL_PARAMS(34, 1), + PLL_PARAMS(40, 1), + PLL_PARAMS(42, 1), + PLL_PARAMS(44, 1), + PLL_PARAMS(45, 1), + PLL_PARAMS(49, 1), + PLL_PARAMS(52, 1), + PLL_PARAMS(54, 1), + PLL_PARAMS(56, 1), + PLL_PARAMS(59, 1), + PLL_PARAMS(60, 1), + PLL_PARAMS(61, 1), + PLL_PARAMS(62, 1), + PLL_PARAMS(64, 1), + PLL_PARAMS(66, 1), + PLL_PARAMS(68, 1), + PLL_PARAMS(71, 1), + PLL_PARAMS(82, 1), + { /* sentinel */ } +}; + static struct clk_regmap meson8b_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -150,6 +172,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { .shift = 29, .width = 1, }, + .table = hdmi_pll_params_table, }, .hw.init = &(struct clk_init_data){ /* sometimes also called "HPLL" or "HPLL PLL" */