| Message ID | 20210226082234.1733-2-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | clk: rockchip: add clock controller for rk3568 | expand |
Hi Elaine, On 2/26/21 9:22 AM, Elaine Zhang wrote: > Document the device tree bindings of the rockchip Rk3568 SoC > clock driver in Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > .../bindings/clock/rockchip,rk3568-cru.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml > new file mode 100644 > index 000000000000..612da341ea67 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: GPL-2.0 This is a new document. Use GPL-2.0 only for a conversion of an existing document in the main kernel. ./scripts/checkpatch.pl --strict 0001-dt-binding-clock-Document-rockchip-rk3568-cru-bindin.patch WARNING: DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause) #21: FILE: Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml:1: +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ROCKCHIP rk3568 Family Clock Control Module Binding > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> - Heiko Stuebner <heiko@sntech.de> Add the maintainer of the clock drivers as well. > + > +description: | > + The RK3568 clock controller generates and supplies clock to various supplies clock This phrase could be improved a bit. (?? generates the clocks signals for ??) > + controllers within the SoC and also implements a reset controller for SoC > + peripherals. > + > +properties: > + compatible: > + enum: > + - rockchip,rk3568-cru > + - rockchip,rk3568-pmucru > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + # Clock Control Module node: > + - | > + pmucru: clock-controller@fdd00000 { > + compatible = "rockchip,rk3568-pmucru"; > + reg = <0x0 0xfdd00000 0x0 0x1000>; Method 1 (easier): reg = <0xfdd00000 0x1000>; This example is 64 bit. The dt_binding_check uses standard 32 bit. Method 2: Add both examples in a subnode. example { #address-cells = <2>; #size-cells = <2>; pmucru {} cru {} } make ARCH=arm64 dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml /Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.example.dt.yaml: example-1: clock-controller@fdd20000:reg:0: [0, 4258398208, 0, 4096] is too long From schema: ~/.local/lib/python3.5/site-packages/dtschema/schemas/reg.yaml /Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.example.dt.yaml: example-0: clock-controller@fdd00000:reg:0: [0, 4258267136, 0, 4096] is too long From schema: ~/.local/lib/python3.5/site-packages/dtschema/schemas/reg.yaml > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + - | > + cru: clock-controller@fdd20000 { > + compatible = "rockchip,rk3568-cru"; > + reg = <0x0 0xfdd20000 0x0 0x1000>; dito > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; >
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml new file mode 100644 index 000000000000..612da341ea67 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROCKCHIP rk3568 Family Clock Control Module Binding + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + +description: | + The RK3568 clock controller generates and supplies clock to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + +properties: + compatible: + enum: + - rockchip,rk3568-cru + - rockchip,rk3568-pmucru + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + };
Document the device tree bindings of the rockchip Rk3568 SoC clock driver in Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../bindings/clock/rockchip,rk3568-cru.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml