From patchwork Fri Feb 26 08:22:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 12106055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64276C4332B for ; Fri, 26 Feb 2021 08:25:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 34B3364EF0 for ; Fri, 26 Feb 2021 08:25:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbhBZIZI (ORCPT ); Fri, 26 Feb 2021 03:25:08 -0500 Received: from lucky1.263xmail.com ([211.157.147.130]:50492 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230090AbhBZIZH (ORCPT ); Fri, 26 Feb 2021 03:25:07 -0500 Received: from localhost (unknown [192.168.167.225]) by lucky1.263xmail.com (Postfix) with ESMTP id D8F71D0163; Fri, 26 Feb 2021 16:22:43 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P5973T140596920432384S1614327760837004_; Fri, 26 Feb 2021 16:22:43 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: zhangqing@rock-chips.com X-SENDER: zhangqing@rock-chips.com X-LOGIN-NAME: zhangqing@rock-chips.com X-FST-TO: mturquette@baylibre.com X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-System-Flag: 0 From: Elaine Zhang To: mturquette@baylibre.com, robh+dt@kernel.org, sboyd@kernel.org, heiko@sntech.de Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cl@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, tony.xie@rock-chips.com, finley.xiao@rock-chips.com, Elaine Zhang Subject: [PATCH v2 1/4] dt-binding: clock: Document rockchip,rk3568-cru bindings Date: Fri, 26 Feb 2021 16:22:31 +0800 Message-Id: <20210226082234.1733-2-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226082234.1733-1-zhangqing@rock-chips.com> References: <20210226082234.1733-1-zhangqing@rock-chips.com> Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Document the device tree bindings of the rockchip Rk3568 SoC clock driver in Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml. Signed-off-by: Elaine Zhang --- .../bindings/clock/rockchip,rk3568-cru.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml new file mode 100644 index 000000000000..612da341ea67 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROCKCHIP rk3568 Family Clock Control Module Binding + +maintainers: + - Elaine Zhang + +description: | + The RK3568 clock controller generates and supplies clock to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + +properties: + compatible: + enum: + - rockchip,rk3568-cru + - rockchip,rk3568-pmucru + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + };