From patchwork Wed Jun 16 14:11:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12325323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 973E8C48BE6 for ; Wed, 16 Jun 2021 14:11:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7FE5760C40 for ; Wed, 16 Jun 2021 14:11:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233850AbhFPONz (ORCPT ); Wed, 16 Jun 2021 10:13:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233908AbhFPONi (ORCPT ); Wed, 16 Jun 2021 10:13:38 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A04FC061226 for ; Wed, 16 Jun 2021 07:11:31 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id l9so1370530wms.1 for ; Wed, 16 Jun 2021 07:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aRbYJUGxam0ZXnZju8D1LdlA08gQ1CtipJh7dYzRZxE=; b=URtkqzq7eQsvp+3xUM0c2/MZeKz+SptdZet/cNznMrs6vqH27HtAWuz+Z/IbDxAmka AWRKXt3iXoJonoq6qs1suYK4ABneq2pNs6thPhexYlnY8rgsoWnBQGN76zKqeVp+qta6 C+U8aDzgk/4qoI/NDs7UsrZ7RbaIJtRRfboK6QFhjSqfgKpK/iPPdiKl7DYHfaMUad9y qyX9Ujlh+dwqZu+rm+gNmcR3vwabmR9dCHIvJpI4pi8rB5alHsoHCfScH46sGvcqrG4q rD7JyO9d7fYr951xDDNl9xqe8amkfvuFtI/DHm0oOMBT8SK6n+3nw/+cB6+ys+SfS6gG wGyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aRbYJUGxam0ZXnZju8D1LdlA08gQ1CtipJh7dYzRZxE=; b=bNY0BCcSspdxWUtUa/sOx9/JwFhCHaQfsclZ6Ksw+Gl/uHN5lQPahsJyB6guXRr9Hl aS17nC7IcRN3GEINFU8ksktY1nE/2b43f+syRMxhvNyRfV0z7fLk7Hg1Gp7DygSrWGpq lFibefVtqDH6RutkVFyFmGo0OHuaLdVOH0axCq1XTwNxSZv92oA+ewP4p0CtZ+CotJYX RVD7DQNVorBOmIyWDsEqB+qVTJL5JnAHrvtBVaoPsyWHlAXbQBkI4sN31bXIkNJKlshZ LGaBSslTeyCKoNd4s/ceJpJbXEaKo6pDe5o03EVymnJNVFTYVp0CkKGqfvGwzo03oC8Q YyeA== X-Gm-Message-State: AOAM5303NWEHUyD3CWpzAFvxQYnYFIoaq86SCRfe7V+JzzRyCR+oo3kF 0I1KgtI47gGEifhVAHjHlAai5Q== X-Google-Smtp-Source: ABdhPJzWJJRAfxGZjvjYyL36Dr7gT78Zyheq+JLOhfuiiXn5Ud8LAwP6cqdik5IJa6dv3g93om5JOw== X-Received: by 2002:a05:600c:4f87:: with SMTP id n7mr121695wmq.9.1623852690211; Wed, 16 Jun 2021 07:11:30 -0700 (PDT) Received: from xps7590.fritz.box ([2a02:2454:3e5:b700:9df7:76e5:7e94:bf1e]) by smtp.gmail.com with ESMTPSA id g83sm1968375wma.10.2021.06.16.07.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jun 2021 07:11:29 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Cc: Robert Foss Subject: [RFC v1 07/11] dt-bindings: clock: Add SM8350 QCOM video clock bindings Date: Wed, 16 Jun 2021 16:11:03 +0200 Message-Id: <20210616141107.291430-8-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210616141107.291430-1-robert.foss@linaro.org> References: <20210616141107.291430-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device tree bindings for video clock controller for SM8350 SoCs. Signed-off-by: Robert Foss --- .../bindings/clock/qcom,videocc.yaml | 2 + .../dt-bindings/clock/qcom,videocc-sm8350.h | 44 +++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..a1dfecbad5c9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -18,6 +18,7 @@ description: | dt-bindings/clock/qcom,videocc-sdm845.h dt-bindings/clock/qcom,videocc-sm8150.h dt-bindings/clock/qcom,videocc-sm8250.h + dt-bindings/clock/qcom,videocc-sm8350.h properties: compatible: @@ -26,6 +27,7 @@ properties: - qcom,sdm845-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc + - qcom,sm8350-videocc clocks: items: diff --git a/include/dt-bindings/clock/qcom,videocc-sm8350.h b/include/dt-bindings/clock/qcom,videocc-sm8350.h new file mode 100644 index 000000000000..531cad2b0ab5 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sm8350.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0C_CLK 5 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS1_CLK 7 +#define VIDEO_CC_MVS1_CLK_SRC 8 +#define VIDEO_CC_MVS1_DIV2_CLK 9 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 10 +#define VIDEO_CC_MVS1C_CLK 11 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 12 +#define VIDEO_CC_SLEEP_CLK 13 +#define VIDEO_CC_SLEEP_CLK_SRC 14 +#define VIDEO_CC_XO_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 +#define VIDEO_PLL0 17 +#define VIDEO_PLL1 18 + +/* VIDEO_CC resets */ +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#define MVS0C_GDSC 0 +#define MVS1C_GDSC 1 +#define MVS0_GDSC 2 +#define MVS1_GDSC 3 + +#endif