diff mbox series

[v2,02/11] drivers: clk: renesas: r9a07g044-cpg: Rename divider table

Message ID 20210624130240.17468-3-biju.das.jz@bp.renesas.com (mailing list archive)
State Superseded, archived
Headers show
Series Update clock definitions | expand

Commit Message

Biju Das June 24, 2021, 1:02 p.m. UTC 
As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it
can be reused.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 v2:
  * New patch
---
 drivers/clk/renesas/r9a07g044-cpg.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Geert Uytterhoeven June 25, 2021, 2:27 p.m. UTC | #1 
Hi Biju,

Thanks for your patch!

On Thu, Jun 24, 2021 at 3:02 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV
> and CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
> clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it

This does not match the actual variable name.
I do like the shorter name, though ;-)

> can be reused.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Apart from that:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -42,12 +42,13 @@ enum clk_ids {
>  };
>
>  /* Divider tables */
> -static const struct clk_div_table dtable_3b[] = {
> +static const struct clk_div_table dtable_common_1_32[] = {
>         {0, 1},
>         {1, 2},
>         {2, 4},
>         {3, 8},
>         {4, 32},
> +       {0, 0},
>  };

Gr{oetje,eeting}s,

                        Geert
Biju Das June 25, 2021, 2:52 p.m. UTC | #2 
Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v2 02/11] drivers: clk: renesas: r9a07g044-cpg: Rename
> divider table
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Thu, Jun 24, 2021 at 3:02 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > As per RZ/G2L HW Manual (Rev.0.50), CPG_PL3A_DDIV,CPG_PL3B_DDIV and
> > CPG_PL2_DDIV(for P0) shares same divider table entries. Rename
> > clk_div_table dtable_3b to clk_div_table dtable_1_32 so that it
> 
> This does not match the actual variable name.
> I do like the shorter name, though ;-)

OK, will change actual variable name with dtable_1_32.

Regards,
Biju

> > can be reused.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Apart from that:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > @@ -42,12 +42,13 @@ enum clk_ids {
> >  };
> >
> >  /* Divider tables */
> > -static const struct clk_div_table dtable_3b[] = {
> > +static const struct clk_div_table dtable_common_1_32[] = {
> >         {0, 1},
> >         {1, 2},
> >         {2, 4},
> >         {3, 8},
> >         {4, 32},
> > +       {0, 0},
> >  };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 50b5269586a4..3b6bde487437 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -42,12 +42,13 @@  enum clk_ids {
 };
 
 /* Divider tables */
-static const struct clk_div_table dtable_3b[] = {
+static const struct clk_div_table dtable_common_1_32[] = {
 	{0, 1},
 	{1, 2},
 	{2, 4},
 	{3, 8},
 	{4, 32},
+	{0, 0},
 };
 
 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
@@ -72,10 +73,10 @@  static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
 	/* Core output clk */
 	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
 	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
-		dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+		dtable_common_1_32, CLK_DIVIDER_HIWORD_MASK),
 	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
 	DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
-		DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
+		DIVPL3B, dtable_common_1_32, CLK_DIVIDER_HIWORD_MASK),
 };
 
 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {