diff mbox series

[next] clk: lmk04832: Fix spelling mistakes in dev_err messages and comments

Message ID 20210629102956.17901-1-colin.king@canonical.com (mailing list archive)
State Accepted, archived
Headers show
Series [next] clk: lmk04832: Fix spelling mistakes in dev_err messages and comments | expand

Commit Message

Colin King June 29, 2021, 10:29 a.m. UTC 
From: Colin Ian King <colin.king@canonical.com>

There are handful of spelling mistakes in two dev_err error messages
and comments. Fix them.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
 drivers/clk/clk-lmk04832.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Stephen Boyd June 30, 2021, 6:19 p.m. UTC | #1 
Quoting Colin King (2021-06-29 03:29:56)
> From: Colin Ian King <colin.king@canonical.com>
> 
> There are handful of spelling mistakes in two dev_err error messages
> and comments. Fix them.
> 
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c
index 0cd76e626c3d..274c1004e938 100644
--- a/drivers/clk/clk-lmk04832.c
+++ b/drivers/clk/clk-lmk04832.c
@@ -519,7 +519,7 @@  static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
 
 	vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
 	if (vco_rate < 0) {
-		dev_err(lmk->dev, "PLL2 parmeters out of range\n");
+		dev_err(lmk->dev, "PLL2 parameters out of range\n");
 		return vco_rate;
 	}
 
@@ -550,7 +550,7 @@  static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
 	if (vco_rate < 0) {
-		dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");
+		dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
 		return vco_rate;
 	}
 
@@ -573,7 +573,7 @@  static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	/*
 	 * PLL2_N registers must be programmed after other PLL2 dividers are
-	 * programed to ensure proper VCO frequency calibration
+	 * programmed to ensure proper VCO frequency calibration
 	 */
 	ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
 			   FIELD_GET(0x030000, n));
@@ -1120,7 +1120,7 @@  static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 		return -EINVAL;
 	}
 
-	/* Enable Duty Cycle Corretion */
+	/* Enable Duty Cycle Correction */
 	if (dclk_div == 1) {
 		ret = regmap_update_bits(lmk->regmap,
 					 LMK04832_REG_CLKOUT_CTRL3(dclk->id),