diff mbox series

[net-next,02/18] drivers: clk: renesas: rzg2l-cpg: Add support to handle MUX clocks

Message ID 20210722141351.13668-3-biju.das.jz@bp.renesas.com (mailing list archive)
State Under Review
Headers show
Series None | expand

Commit Message

Biju Das July 22, 2021, 2:13 p.m. UTC
Add support to handle mux clocks inorder to select a clock source
from multiple sources.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 24 ++++++++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.h |  9 +++++++++
 2 files changed, 33 insertions(+)

Comments

Sergei Shtylyov July 23, 2021, 10:26 a.m. UTC | #1
Hello!

On 22.07.2021 17:13, Biju Das wrote:

> Add support to handle mux clocks inorder to select a clock source

    In order.

> from multiple sources.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>   drivers/clk/renesas/rzg2l-cpg.c | 24 ++++++++++++++++++++++++
>   drivers/clk/renesas/rzg2l-cpg.h |  9 +++++++++
>   2 files changed, 33 insertions(+)
> 
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> index 3b3b2c3347f3..491b10da5766 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -130,6 +130,27 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
>   	return clk_hw->clk;
>   }
>   
> +static struct clk * __init
> +rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
> +			   void __iomem *base,
> +			   struct rzg2l_cpg_priv *priv)
> +{
> +	const struct clk_hw *clk_hw;
> +
> +	clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
> +					  core->parent_names, core->num_parents,
> +					  core->flag,
> +					  base + GET_REG_OFFSET(core->conf),
> +					  GET_SHIFT(core->conf),
> +					  GET_WIDTH(core->conf),
> +					  core->mux_flags, &priv->rmw_lock);
> +

    Empty line is hardly needed here...

> +	if (IS_ERR(clk_hw))
> +		return ERR_CAST(clk_hw);
> +
> +	return clk_hw->clk;
> +}
> +
>   struct pll_clk {
>   	struct clk_hw hw;
>   	unsigned int conf;
[...]

MBR, Sergei
Biju Das July 23, 2021, 12:12 p.m. UTC | #2
Hi Sergei,

Thanks for the review.

> Subject: Re: [PATCH net-next 02/18] drivers: clk: renesas: rzg2l-cpg: Add
> support to handle MUX clocks
> 
> Hello!
> 
> On 22.07.2021 17:13, Biju Das wrote:
> 
> > Add support to handle mux clocks inorder to select a clock source
> 
>     In order.

Ok.
> 
> > from multiple sources.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >   drivers/clk/renesas/rzg2l-cpg.c | 24 ++++++++++++++++++++++++
> >   drivers/clk/renesas/rzg2l-cpg.h |  9 +++++++++
> >   2 files changed, 33 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/rzg2l-cpg.c
> > b/drivers/clk/renesas/rzg2l-cpg.c index 3b3b2c3347f3..491b10da5766
> > 100644
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -130,6 +130,27 @@ rzg2l_cpg_div_clk_register(const struct
> cpg_core_clk *core,
> >   	return clk_hw->clk;
> >   }
> >
> > +static struct clk * __init
> > +rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
> > +			   void __iomem *base,
> > +			   struct rzg2l_cpg_priv *priv)
> > +{
> > +	const struct clk_hw *clk_hw;
> > +
> > +	clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
> > +					  core->parent_names, core->num_parents,
> > +					  core->flag,
> > +					  base + GET_REG_OFFSET(core->conf),
> > +					  GET_SHIFT(core->conf),
> > +					  GET_WIDTH(core->conf),
> > +					  core->mux_flags, &priv->rmw_lock);
> > +
> 
>     Empty line is hardly needed here...

OK. Will fix it in next version.

Cheers,
Biju
Geert Uytterhoeven July 26, 2021, 10:53 a.m. UTC | #3
Hi Biju,


On Thu, Jul 22, 2021 at 4:14 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add support to handle mux clocks inorder to select a clock source
> from multiple sources.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -43,6 +43,7 @@ struct cpg_core_clk {
>         const struct clk_div_table *dtable;
>         const char * const *parent_names;
>         int flag;
> +       int mux_flags;
>         int num_parents;
>  };
>

I'd move SEL_PLL_PACK() from [PATCH 03/18] here, as it applies to
"_conf" in DEF_MUX() below.

> @@ -54,6 +55,9 @@ enum clk_types {
>
>         /* Clock with divider */
>         CLK_TYPE_DIV,
> +
> +       /* Clock with clock source selector */
> +       CLK_TYPE_MUX,
>  };
>
>  #define DEF_TYPE(_name, _id, _type...) \
> @@ -69,6 +73,11 @@ enum clk_types {
>  #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
>         DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
>                  .parent = _parent, .dtable = _dtable, .flag = _flag)
> +#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
> +               _mux_flags) \
> +       DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
> +                .parent_names = _parent_names, .num_parents = _num_parents, \
> +                .flag = _flag, .mux_flags = _mux_flags)
>
>  /**
>   * struct rzg2l_mod_clk - Module Clocks definitions

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Biju Das July 26, 2021, 12:23 p.m. UTC | #4
Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH net-next 02/18] drivers: clk: renesas: rzg2l-cpg: Add
> support to handle MUX clocks
> 
> Hi Biju,
> 
> 
> On Thu, Jul 22, 2021 at 4:14 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add support to handle mux clocks inorder to select a clock source from
> > multiple sources.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> > --- a/drivers/clk/renesas/rzg2l-cpg.h
> > +++ b/drivers/clk/renesas/rzg2l-cpg.h
> > @@ -43,6 +43,7 @@ struct cpg_core_clk {
> >         const struct clk_div_table *dtable;
> >         const char * const *parent_names;
> >         int flag;
> > +       int mux_flags;
> >         int num_parents;
> >  };
> >
> 
> I'd move SEL_PLL_PACK() from [PATCH 03/18] here, as it applies to "_conf"
> in DEF_MUX() below.

OK. Will move in this patch

Regards,
Biju

> 
> > @@ -54,6 +55,9 @@ enum clk_types {
> >
> >         /* Clock with divider */
> >         CLK_TYPE_DIV,
> > +
> > +       /* Clock with clock source selector */
> > +       CLK_TYPE_MUX,
> >  };
> >
> >  #define DEF_TYPE(_name, _id, _type...) \ @@ -69,6 +73,11 @@ enum
> > clk_types {  #define DEF_DIV(_name, _id, _parent, _conf, _dtable,
> > _flag) \
> >         DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
> >                  .parent = _parent, .dtable = _dtable, .flag = _flag)
> > +#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag,
> \
> > +               _mux_flags) \
> > +       DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
> > +                .parent_names = _parent_names, .num_parents =
> _num_parents, \
> > +                .flag = _flag, .mux_flags = _mux_flags)
> >
> >  /**
> >   * struct rzg2l_mod_clk - Module Clocks definitions
> 
> With the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3b3b2c3347f3..491b10da5766 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -130,6 +130,27 @@  rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
 	return clk_hw->clk;
 }
 
+static struct clk * __init
+rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
+			   void __iomem *base,
+			   struct rzg2l_cpg_priv *priv)
+{
+	const struct clk_hw *clk_hw;
+
+	clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
+					  core->parent_names, core->num_parents,
+					  core->flag,
+					  base + GET_REG_OFFSET(core->conf),
+					  GET_SHIFT(core->conf),
+					  GET_WIDTH(core->conf),
+					  core->mux_flags, &priv->rmw_lock);
+
+	if (IS_ERR(clk_hw))
+		return ERR_CAST(clk_hw);
+
+	return clk_hw->clk;
+}
+
 struct pll_clk {
 	struct clk_hw hw;
 	unsigned int conf;
@@ -288,6 +309,9 @@  rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
 		clk = rzg2l_cpg_div_clk_register(core, priv->clks,
 						 priv->base, priv);
 		break;
+	case CLK_TYPE_MUX:
+		clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
+		break;
 	default:
 		goto fail;
 	}
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 63695280ce8b..148db5de253b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -43,6 +43,7 @@  struct cpg_core_clk {
 	const struct clk_div_table *dtable;
 	const char * const *parent_names;
 	int flag;
+	int mux_flags;
 	int num_parents;
 };
 
@@ -54,6 +55,9 @@  enum clk_types {
 
 	/* Clock with divider */
 	CLK_TYPE_DIV,
+
+	/* Clock with clock source selector */
+	CLK_TYPE_MUX,
 };
 
 #define DEF_TYPE(_name, _id, _type...) \
@@ -69,6 +73,11 @@  enum clk_types {
 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
 	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
 		 .parent = _parent, .dtable = _dtable, .flag = _flag)
+#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
+		_mux_flags) \
+	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
+		 .parent_names = _parent_names, .num_parents = _num_parents, \
+		 .flag = _flag, .mux_flags = _mux_flags)
 
 /**
  * struct rzg2l_mod_clk - Module Clocks definitions