| Message ID | 20210910184147.336618-3-paul.kocialkowski@bootlin.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Allwinner A31/A83T MIPI CSI-2 Support and A31 ISP Support | expand |
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 776913b3f85f..a77b63362a1d 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -622,6 +622,9 @@ csi1: camera@1cb4000 { clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_CSI>; status = "disabled"; + + assigned-clocks = <&ccu CLK_CSI1_SCLK>; + assigned-clock-parents = <&ccu CLK_PLL_ISP>; }; gic: interrupt-controller@1c81000 {
At reset time, the CSI module clock is parented to the video PLL, which is used by the display engine. While the CSI module clock needs to be clocked at precisely 297 MHz, the display engine will need to adjust its clock usage depending on the display pixel rate. As a result, the video PLL may be reconfigured to fit the need of the display engine, which will break the CSI hardware. A good way to work around this is to reparent the CSI module clock to the ISP PLL (like it is done in the Allwinner SDK). Do this using the device-tree assigned-clock properties. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 3 +++ 1 file changed, 3 insertions(+)