From patchwork Sat Sep 11 13:19:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 12486391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA44CC433FE for ; Sat, 11 Sep 2021 13:21:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 945B4611CC for ; Sat, 11 Sep 2021 13:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237087AbhIKNW5 (ORCPT ); Sat, 11 Sep 2021 09:22:57 -0400 Received: from relay04.th.seeweb.it ([5.144.164.165]:57071 "EHLO relay04.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237244AbhIKNUq (ORCPT ); Sat, 11 Sep 2021 09:20:46 -0400 Received: from Marijn-Arch-PC.localdomain (94-209-165-62.cable.dynamic.v4.ziggo.nl [94.209.165.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 1218E1F50A; Sat, 11 Sep 2021 15:19:31 +0200 (CEST) From: Marijn Suijten To: phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Marijn Suijten , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Dmitry Baryshkov , Abhinav Kumar , Jonathan Marek , Matthias Kaehlcke , Douglas Anderson , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v3 2/2] clk: qcom: gcc-sdm660: Remove transient global "xo" clock Date: Sat, 11 Sep 2021 15:19:21 +0200 Message-Id: <20210911131922.387964-3-marijn.suijten@somainline.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210911131922.387964-1-marijn.suijten@somainline.org> References: <20210911131922.387964-1-marijn.suijten@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The DSI PHY/PLL was relying on a global "xo" clock to be found, but the real clock is named "xo_board" in the DT. The standard nowadays is to never use global clock names anymore but require the firmware (DT) to provide every clock binding explicitly with .fw_name. The DSI PLLs have since been converted to this mechanism (specifically 14nm for SDM660) and this transient clock can now be removed. This issue was originally discovered in: https://lore.kernel.org/linux-arm-msm/386db1a6-a1cd-3c7d-a88e-dc83f8a1be96@somainline.org/ and prevented the removal of "xo" at that time. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Acked-by: Stephen Boyd --- drivers/clk/qcom/gcc-sdm660.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 7fb5adf7fa01..429d12193146 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -37,19 +37,6 @@ enum { P_GPLL1_EARLY_DIV, }; -static struct clk_fixed_factor xo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data){ - .name = "xo", - .parent_data = &(const struct clk_parent_data) { - .fw_name = "xo" - }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - static struct clk_alpha_pll gpll0_early = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], @@ -2280,7 +2267,6 @@ static struct gdsc pcie_0_gdsc = { }; static struct clk_hw *gcc_sdm660_hws[] = { - &xo.hw, &gpll0_early_div.hw, &gpll1_early_div.hw, };