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[84.20.244.219]) by smtp.gmail.com with ESMTPSA id g131sm14752780wme.22.2021.09.20.07.49.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:49:59 -0700 (PDT) From: Krzysztof Kozlowski To: Michael Turquette , Stephen Boyd , Rob Herring , Palmer Dabbelt , Paul Walmsley , Albert Ou , Zong Li , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] dt-bindings: clock: fu740-prci: add reset-cells Date: Mon, 20 Sep 2021 16:49:44 +0200 Message-Id: <20210920144944.162431-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The SiFive FU740 Power Reset Clock Interrupt Controller is a reset line provider so add respective reset-cells property to fix: arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dt.yaml: clock-controller@10000000: '#reset-cells' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Acked-by: Palmer Dabbelt --- .../devicetree/bindings/clock/sifive/fu740-prci.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml index e17143cac316..252085a0cf65 100644 --- a/Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml +++ b/Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml @@ -42,6 +42,9 @@ properties: "#clock-cells": const: 1 + "#reset-cells": + const: 1 + required: - compatible - reg @@ -57,4 +60,5 @@ examples: reg = <0x10000000 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; };