| Message ID | 20210922112405.26413-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [v2,1/2] clk: renesas: r9a07g044: Add IA55_CLK and DMAC_ACLK | expand |
On Wed, Sep 22, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value > 0 means clock is not supplied and 1 means clock is supplied. > This patch fixes the issue by removing the inverted logic. > > Fixing the above, triggered following 2 issues > > 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK. > Fixed this issue by adding these clocks as critical clocks. > > 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK. > So will provide a fix in the DMA driver to turn on DMA_PCLK. > > Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue as a fix in renesas-clk-for-v5.15. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 089b6cb64c1f..270c530e8017 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -453,7 +453,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) value = readl(priv->base + CLK_MON_R(clock->off)); - return !(value & bitmask); + return value & bitmask; } static const struct clk_ops rzg2l_mod_clock_ops = {
As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value 0 means clock is not supplied and 1 means clock is supplied. This patch fixes the issue by removing the inverted logic. Fixing the above, triggered following 2 issues 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK. Fixed this issue by adding these clocks as critical clocks. 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK. So will provide a fix in the DMA driver to turn on DMA_PCLK. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v1->v2: * Incorporated Sergei's review comment by removing Parens. --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)