From patchwork Wed Oct 6 06:12:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12538679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D87BC43217 for ; Wed, 6 Oct 2021 06:12:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E18E6115A for ; Wed, 6 Oct 2021 06:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237320AbhJFGOI (ORCPT ); Wed, 6 Oct 2021 02:14:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236829AbhJFGOD (ORCPT ); Wed, 6 Oct 2021 02:14:03 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FB6CC061760; Tue, 5 Oct 2021 23:12:11 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id r10so5180011wra.12; Tue, 05 Oct 2021 23:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1KLm/UJPYCVCyNtfvETKNp1rfk93uLu7qVrvjdeZZXs=; b=X44T/lPel1S7KxSPvTnlWaNvJ1OgLA3w4idDroLy+/CMHRs8b8FxJtJ0jERLqJcAEB 7ftKiKQbvLk+/sAceBf8Q933r3fyGtZniOphBQlEkotEGAlvZfJZa0SkmSBfvCPZwrrc A464CHjo3CZLaTPU+ElLSk2W/h6N+s6VKyhVno0NKbH6Odp8CSoOEH2dwEG8QvfED8ih oQWfnW8gI76UUUUn8auaU8+gG6TFec0VGIHI0rx9tY3v5olK0WETJO831d8w/XauNN2M y60TRqWgV3JzpIG08gYixAKu2LEozbmeakBGr/MC6Qjf3pClzLGCCTmY/zfQaG+AFXTc LAtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1KLm/UJPYCVCyNtfvETKNp1rfk93uLu7qVrvjdeZZXs=; b=g7WgFBo6TCoz4AfQbi2vX5FeJoFJ0PLxuJx/IDHYWux75qNC5SuDU8FHReNlq37Zwn pymTcPSV0rNzyyM96v6ZKs6b57G5Il1rBQU2v07k4OSYm3wxfj8k49n8X0sCNoK8gvqm vaz6hY92K8SfLReGpiHsdJE2FZsmVlBuZNWKhQAXY9Rd4kaT+K4WrX8H+qniJWsdw4k1 07jBCHzCzC5o+A2Pbx+/ezSvRt3EUVqjgf6TdSsjfg8Ygc2jR8R7XpgEwMU+JHOmEbx2 8jS8DDETtcYeCxejgXhhds6TfgPKWEL47g7bWPg2NiDYMZmc2DshiscLrr06pmx13+Gp xSfQ== X-Gm-Message-State: AOAM53284VCKMFXMRSePSAvOCJlqul/5Qk33RRXmmDjJMA6yW4tmZLX3 nvEG3xh7O9Nax/C5U8YXJ/U= X-Google-Smtp-Source: ABdhPJwNea3SPVzx29nCKNcRJnbkZu9QqMxzoIhht6EivaDF2CPB6tfCaL2DTlVZ5t5FLqWhWEgWaw== X-Received: by 2002:adf:e985:: with SMTP id h5mr672621wrm.367.1633500729609; Tue, 05 Oct 2021 23:12:09 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id e8sm3893071wme.46.2021.10.05.23.12.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Oct 2021 23:12:09 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH 3/4] clk: ralink: make system controller node a reset provider Date: Wed, 6 Oct 2021 08:12:03 +0200 Message-Id: <20211006061204.2854-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006061204.2854-1-sergio.paracuellos@gmail.com> References: <20211006061204.2854-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..67ccc9582c46 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static inline struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -1; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -1; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = kzalloc(sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + pr_err("Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),