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[83.54.181.252]) by smtp.gmail.com with ESMTPSA id e14sm10801985wrw.33.2021.10.06.04.23.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Oct 2021 04:23:09 -0700 (PDT) From: Sergio Paracuellos To: sboyd@kernel.org Cc: linux-clk@vger.kernel.org, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, robh+dt@kernel.org, linux-staging@lists.linux.dev, neil@brown.name, linux-kernel@vger.kernel.org, john@phrozen.org Subject: [PATCH v2 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property Date: Wed, 6 Oct 2021 13:23:04 +0200 Message-Id: <20211006112306.4691-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211006112306.4691-1-sergio.paracuellos@gmail.com> References: <20211006112306.4691-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Make system controller a reset provider for all the peripherals in the MT7621 SoC adding '#reset-cells' property. Signed-off-by: Sergio Paracuellos Acked-by: Rob Herring --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml index 915f84efd763..0c0b0ae5e2ac 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml @@ -22,6 +22,11 @@ description: | The clocks are provided inside a system controller node. + This node is also a reset provider for all the peripherals. + + Reset related bits are defined in: + [2]: . + properties: compatible: items: @@ -37,6 +42,12 @@ properties: clocks. const: 1 + "#reset-cells": + description: + The first cell indicates the reset bit within the register, see + [2] for available resets. + const: 1 + ralink,memctl: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -61,6 +72,7 @@ examples: compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m",