From patchwork Sat Oct 30 14:20:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12594417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F044C433F5 for ; Sat, 30 Oct 2021 14:20:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 550E46101E for ; Sat, 30 Oct 2021 14:20:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230071AbhJ3OWr (ORCPT ); Sat, 30 Oct 2021 10:22:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230303AbhJ3OWp (ORCPT ); Sat, 30 Oct 2021 10:22:45 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54C17C061570; Sat, 30 Oct 2021 07:20:15 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id v17so21170323wrv.9; Sat, 30 Oct 2021 07:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F5x1oqtvVP/PGtFgO2U9FSpcbZxZK7r+xhICFV95IKo=; b=KkVOt+LAZlq1nTiNsYPYr/MlwIStQYb0R/EKITJAyNqUIykthIosrTrJEUoLSPg/K7 8REM4Wv1pQ7EXJp+X58Z6e4/jJ1A3LOK+UpDA4UkIgaM48ULQx5iLbDm1MRs8LGpsHD1 yrEg9r8WgVR376MgDhP9qEI/0rYXOLzn74oqOsXnv9koKgMdQOyxLazmq5jkmfA3zH0g jAzC/Qyt4FWLKHqbNEMWU5rG/89MhgURScmA0yfcWyLZ/orKHZQt/bJAVXMbO2KUyZJf 8g3ixTTh+oQFWW9+qyrPrhOH9dZuZwkWnZN8cB6Zoq+sUlBCOIpQMs3XuLVydRSZ/7SN yFzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F5x1oqtvVP/PGtFgO2U9FSpcbZxZK7r+xhICFV95IKo=; b=ymoNDWkmqUZiEGWj2jODFcQZly3+Roo60r4NgAEerTdmjJ/d2OuH2UYbv6xt9aubMt siB9eMG8FzBPIpWAD0QVvWsKqZ0/Assi8NLGSV9KRZnVPZ7wvXfgGQqWuC/m9UCbrZUC WdyDHXw1kiW7Ec3qEQH9YiWBtHA1qJMP4UBpOP08jzsdLDh83mRunrB15iryL1quzoyO IQk+kYLTHCh049s9JsyF5gofgzhQE1X0e18BarAMMMGCWyuDbZJhTaRNDyV4Z1ebo4Cp +s5lw5prPPabaBnAfSH4F/1rQkHvfbI5AfEDRDiRw34c7JNCSa5i9BPgD5VjNR68SErp F/Cw== X-Gm-Message-State: AOAM532XbAyiwvUOA7JCse4cQ5HXhZUZlEvnLn9f9EtZ/duCGye59x4+ Ajr1oXYy8CUdRUiYivzUrWrrKe5gce7deQ== X-Google-Smtp-Source: ABdhPJxtz+uMrR/oOgJ8L1C/5tOkqi1DpssmgGY8Xkz39G7bLAlUp5zXg1vB25tIKREwgogIObk//Q== X-Received: by 2002:a05:6000:2a4:: with SMTP id l4mr23395325wry.221.1635603613662; Sat, 30 Oct 2021 07:20:13 -0700 (PDT) Received: from localhost.localdomain (252.red-83-54-181.dynamicip.rima-tde.net. [83.54.181.252]) by smtp.gmail.com with ESMTPSA id m12sm8208521wrq.69.2021.10.30.07.20.12 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 30 Oct 2021 07:20:13 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, sboyd@kernel.org, john@phrozen.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name Subject: [PATCH v3 3/4] clk: ralink: make system controller node a reset provider Date: Sat, 30 Oct 2021 16:20:06 +0200 Message-Id: <20211030142007.27085-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211030142007.27085-1-sergio.paracuellos@gmail.com> References: <20211030142007.27085-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MT7621 system controller node is already providing the clocks for the whole system but must also serve as a reset provider. Hence, add reset controller related code to the clock driver itself. Signed-off-by: Sergio Paracuellos --- drivers/clk/ralink/clk-mt7621.c | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c index a2c045390f00..f149dd2d1325 100644 --- a/drivers/clk/ralink/clk-mt7621.c +++ b/drivers/clk/ralink/clk-mt7621.c @@ -11,14 +11,17 @@ #include #include #include +#include #include #include +#include /* Configuration registers */ #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 #define SYSC_REG_CLKCFG0 0x2c #define SYSC_REG_CLKCFG1 0x30 +#define SYSC_REG_RESET_CTRL 0x34 #define SYSC_REG_CUR_CLK_STS 0x44 #define MEMC_REG_CPU_PLL 0x648 @@ -398,6 +401,76 @@ static void __init mt7621_clk_init(struct device_node *node) } CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init); +struct mt7621_rst { + struct reset_controller_dev rcdev; + struct regmap *sysc; +}; + +static inline struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev) +{ + return container_of(dev, struct mt7621_rst, rcdev); +} + +static int mt7621_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -1; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); +} + +static int mt7621_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mt7621_rst *data = to_mt7621_rst(rcdev); + struct regmap *sysc = data->sysc; + + if (id == MT7621_RST_SYS) + return -1; + + return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); +} + +static int mt7621_reset_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mt7621_assert_device(rcdev, id); + if (ret < 0) + return ret; + + return mt7621_deassert_device(rcdev, id); +} + +static const struct reset_control_ops reset_ops = { + .reset = mt7621_reset_device, + .assert = mt7621_assert_device, + .deassert = mt7621_deassert_device +}; + +static int mt7621_reset_init(struct device *dev, struct regmap *sysc) +{ + struct mt7621_rst *rst_data; + + rst_data = kzalloc(sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->sysc = sysc; + rst_data->rcdev.ops = &reset_ops; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.nr_resets = 32; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.of_node = dev_of_node(dev); + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int mt7621_clk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -424,6 +497,12 @@ static int mt7621_clk_probe(struct platform_device *pdev) return ret; } + ret = mt7621_reset_init(dev, priv->sysc); + if (ret) { + dev_err(dev, "Could not init reset controller\n"); + return ret; + } + count = ARRAY_SIZE(mt7621_clks_base) + ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates); clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),