From patchwork Thu Nov 11 12:11:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12614723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA6F5C433FE for ; Thu, 11 Nov 2021 12:11:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D04CA6128E for ; Thu, 11 Nov 2021 12:11:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232318AbhKKMOm (ORCPT ); Thu, 11 Nov 2021 07:14:42 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:45678 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232855AbhKKMOl (ORCPT ); Thu, 11 Nov 2021 07:14:41 -0500 X-IronPort-AV: E=Sophos;i="5.87,226,1631545200"; d="scan'208";a="99922508" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 11 Nov 2021 21:11:52 +0900 Received: from localhost.localdomain (unknown [10.226.93.91]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0343C400F783; Thu, 11 Nov 2021 21:11:49 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 1/4] clk: renesas: rzg2l: Add CPG_PL1_DDIV macro Date: Thu, 11 Nov 2021 12:11:41 +0000 Message-Id: <20211111121144.11131-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211111121144.11131-1-biju.das.jz@bp.renesas.com> References: <20211111121144.11131-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU frequency. Define CPG_PL1_DDIV, so that we can register it as a clock divider in later patch. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- drivers/clk/renesas/rzg2l-cpg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 484c7cee2629..fce4a8f35410 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -9,6 +9,7 @@ #ifndef __RENESAS_RZG2L_CPG_H__ #define __RENESAS_RZG2L_CPG_H__ +#define CPG_PL1_DDIV (0x200) #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) #define CPG_PL2SDHI_DSEL (0x218) @@ -29,6 +30,7 @@ #define DDIV_PACK(offset, bitpos, size) \ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) +#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)