| Message ID | 20211118080634.165275-1-deng.changcheng@zte.com.cn (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [v2] clk: imx: Use div64_ul instead of do_div | expand |
On 21-11-18 08:06:34, cgel.zte@gmail.com wrote: > From: Changcheng Deng <deng.changcheng@zte.com.cn> > > do_div() does a 64-by-32 division. Here the divisor is an unsigned long > which on some platforms is 64 bit wide. So use div64_ul instead of do_div > to avoid a possible truncation. > > Reported-by: Zeal Robot <zealci@zte.com.cn> > Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/clk-pllv3.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c > index 20ee9611ba6e..55497e0585a6 100644 > --- a/drivers/clk/imx/clk-pllv3.c > +++ b/drivers/clk/imx/clk-pllv3.c > @@ -247,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, > div = rate / parent_rate; > temp64 = (u64) (rate - div * parent_rate); > temp64 *= mfd; > - do_div(temp64, parent_rate); > + temp64 = div64_ul(temp64, parent_rate); > mfn = temp64; > > temp64 = (u64)parent_rate; > @@ -277,7 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, > div = rate / parent_rate; > temp64 = (u64) (rate - div * parent_rate); > temp64 *= mfd; > - do_div(temp64, parent_rate); > + temp64 = div64_ul(temp64, parent_rate); > mfn = temp64; > > val = readl_relaxed(pll->base); > @@ -334,7 +334,7 @@ static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( > /* rate = parent_rate * (mfi + mfn/mfd) */ > temp64 = rate - parent_rate * mf.mfi; > temp64 *= mf.mfd; > - do_div(temp64, parent_rate); > + temp64 = div64_ul(temp64, parent_rate); > mf.mfn = temp64; > } > > -- > 2.25.1 >
On 21-11-18 08:06:34, cgel.zte@gmail.com wrote: > From: Changcheng Deng <deng.changcheng@zte.com.cn> > > do_div() does a 64-by-32 division. Here the divisor is an unsigned long > which on some platforms is 64 bit wide. So use div64_ul instead of do_div > to avoid a possible truncation. > > Reported-by: Zeal Robot <zealci@zte.com.cn> > Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> For future patches, please do not send the new version as a reply to the older one. It gets confusing. Applied, thanks. > --- > drivers/clk/imx/clk-pllv3.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c > index 20ee9611ba6e..55497e0585a6 100644 > --- a/drivers/clk/imx/clk-pllv3.c > +++ b/drivers/clk/imx/clk-pllv3.c > @@ -247,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, > div = rate / parent_rate; > temp64 = (u64) (rate - div * parent_rate); > temp64 *= mfd; > - do_div(temp64, parent_rate); > + temp64 = div64_ul(temp64, parent_rate); > mfn = temp64; > > temp64 = (u64)parent_rate; > @@ -277,7 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, > div = rate / parent_rate; > temp64 = (u64) (rate - div * parent_rate); > temp64 *= mfd; > - do_div(temp64, parent_rate); > + temp64 = div64_ul(temp64, parent_rate); > mfn = temp64; > > val = readl_relaxed(pll->base); > @@ -334,7 +334,7 @@ static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( > /* rate = parent_rate * (mfi + mfn/mfd) */ > temp64 = rate - parent_rate * mf.mfi; > temp64 *= mf.mfd; > - do_div(temp64, parent_rate); > + temp64 = div64_ul(temp64, parent_rate); > mf.mfn = temp64; > } > > -- > 2.25.1 >
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 20ee9611ba6e..55497e0585a6 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -247,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mfn = temp64; temp64 = (u64)parent_rate; @@ -277,7 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mfn = temp64; val = readl_relaxed(pll->base); @@ -334,7 +334,7 @@ static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( /* rate = parent_rate * (mfi + mfn/mfd) */ temp64 = rate - parent_rate * mf.mfi; temp64 *= mf.mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mf.mfn = temp64; }