From patchwork Mon Jan 10 00:59:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chun-Jie Chen X-Patchwork-Id: 12708032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 127D5C433F5 for ; Mon, 10 Jan 2022 00:59:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237655AbiAJA7q (ORCPT ); Sun, 9 Jan 2022 19:59:46 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:41348 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237665AbiAJA7b (ORCPT ); Sun, 9 Jan 2022 19:59:31 -0500 X-UUID: 0eace77e04f34a8a9c97eb8f3321413c-20220110 X-UUID: 0eace77e04f34a8a9c97eb8f3321413c-20220110 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 266559539; Mon, 10 Jan 2022 08:59:28 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 10 Jan 2022 08:59:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 10 Jan 2022 08:59:26 +0800 From: Chun-Jie Chen To: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring CC: , , , , , , , Chun-Jie Chen Subject: [v2 3/3] clk: mediatek: Integrate vppsys with mtk-mmsys in MT8195 Date: Mon, 10 Jan 2022 08:59:02 +0800 Message-ID: <20220110005902.27148-4-chun-jie.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220110005902.27148-1-chun-jie.chen@mediatek.com> References: <20220110005902.27148-1-chun-jie.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Integrate vpp0 and vpp1 with mtk-mmsys driver which will populate device by platform_device_register_data to start vppsys clock driver. Signed-off-by: Chun-Jie Chen --- drivers/clk/mediatek/clk-mt8195-vpp0.c | 42 +++++++++++++++++--------- drivers/clk/mediatek/clk-mt8195-vpp1.c | 42 +++++++++++++++++--------- 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c index c3241466a8d0..68c375bfce8b 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -86,25 +86,39 @@ static const struct mtk_gate vpp0_clks[] = { GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3), }; -static const struct mtk_clk_desc vpp0_desc = { - .clks = vpp0_clks, - .num_clks = ARRAY_SIZE(vpp0_clks), -}; +static int clk_mt8195_vpp0_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; + struct clk_onecell_data *clk_data; + int r; -static const struct of_device_id of_match_clk_mt8195_vpp0[] = { - { - .compatible = "mediatek,mt8195-vppsys0", - .data = &vpp0_desc, - }, { - /* sentinel */ - } -}; + clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); + if (r) + goto free_vpp0_data; + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto unregister_clk; + + return r; + +unregister_clk: + mtk_clk_unregister(clk_data); + +free_vpp0_data: + mtk_free_clk_data(clk_data); + return r; +} static struct platform_driver clk_mt8195_vpp0_drv = { - .probe = mtk_clk_simple_probe, + .probe = clk_mt8195_vpp0_probe, .driver = { .name = "clk-mt8195-vpp0", - .of_match_table = of_match_clk_mt8195_vpp0, }, }; builtin_platform_driver(clk_mt8195_vpp0_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c index ce0b9a40a179..237077c60f54 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -84,25 +84,39 @@ static const struct mtk_gate vpp1_clks[] = { GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26), }; -static const struct mtk_clk_desc vpp1_desc = { - .clks = vpp1_clks, - .num_clks = ARRAY_SIZE(vpp1_clks), -}; +static int clk_mt8195_vpp1_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; + struct clk_onecell_data *clk_data; + int r; -static const struct of_device_id of_match_clk_mt8195_vpp1[] = { - { - .compatible = "mediatek,mt8195-vppsys1", - .data = &vpp1_desc, - }, { - /* sentinel */ - } -}; + clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); + if (r) + goto free_vpp1_data; + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto unregister_clk; + + return r; + +unregister_clk: + mtk_clk_unregister(clk_data); + +free_vpp1_data: + mtk_free_clk_data(clk_data); + return r; +} static struct platform_driver clk_mt8195_vpp1_drv = { - .probe = mtk_clk_simple_probe, + .probe = clk_mt8195_vpp1_probe, .driver = { .name = "clk-mt8195-vpp1", - .of_match_table = of_match_clk_mt8195_vpp1, }, }; builtin_platform_driver(clk_mt8195_vpp1_drv);