| Message ID | 20220112174612.10773-5-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | RFC, archived |
| Headers | show |
| Series | Add RZ/G2L Display support | expand |
Hi Biju, On Wed, Jan 12, 2022 at 6:46 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add support for M1 clock which is sourced from FOUTPOSTDIV. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- a/drivers/clk/renesas/r9a07g044-cpg.c > +++ b/drivers/clk/renesas/r9a07g044-cpg.c The above looks correct to me, so Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > @@ -353,4 +362,7 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { > /* Resets */ > .resets = r9a07g044_resets, > .num_resets = ARRAY_SIZE(r9a07g044_resets), > + > + /* lcdc mode for PLL5 settings*/ > + .pll5_lcdc_dsi_mode = true, > }; This is the part I don't like, but I guess you could imagine ;-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. > Subject: Re: [RFC 04/28] clk: renesas: r9a07g044: Add M1 clock support > > Hi Biju, > > On Wed, Jan 12, 2022 at 6:46 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Add support for M1 clock which is sourced from FOUTPOSTDIV. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r9a07g044-cpg.c > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > > The above looks correct to me, so > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > @@ -353,4 +362,7 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { > > /* Resets */ > > .resets = r9a07g044_resets, > > .num_resets = ARRAY_SIZE(r9a07g044_resets), > > + > > + /* lcdc mode for PLL5 settings*/ > > + .pll5_lcdc_dsi_mode = true, > > }; > > This is the part I don't like, but I guess you could imagine ;-) Agreed, Will remove this. Cheers, Biju
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 79042bf46fe8..d24e3c73b2bd 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -39,6 +39,8 @@ enum clk_ids { CLK_DIV_PLL3_C, CLK_PLL4, CLK_PLL5, + CLK_PLL5_FOUTPOSTDIV, + CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUT3, CLK_PLL5_250, CLK_PLL6, @@ -51,6 +53,7 @@ enum clk_ids { CLK_SD0_DIV4, CLK_SD1_DIV4, CLK_SEL_GPU2, + CLK_SEL_PLL5_4, /* Module Clocks */ MOD_CLK_BASE, @@ -76,6 +79,7 @@ static const struct clk_div_table dtable_1_32[] = { /* Mux clock tables */ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; +static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; @@ -120,6 +124,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), + DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), + DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), + DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, + sel_pll5_4, ARRAY_SIZE(sel_pll5_4)), /* Core output clk */ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, @@ -147,6 +155,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), }; static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { @@ -353,4 +362,7 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Resets */ .resets = r9a07g044_resets, .num_resets = ARRAY_SIZE(r9a07g044_resets), + + /* lcdc mode for PLL5 settings*/ + .pll5_lcdc_dsi_mode = true, };
Add support for M1 clock which is sourced from FOUTPOSTDIV. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)