| Message ID | 20220221181322.5486-1-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [v2,1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG | expand |
Quoting Taniya Das (2022-02-21 10:13:21) > The display pixel clock has a requirement on certain newer platforms to > support M/N as (2/3) and the final D value calculated results in > underflow errors. > As the current implementation does not check for D value is within > the accepted range for a given M & N value. Update the logic to > calculate the final D value based on the range. > > Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- > [v2] > * Update the if else check with clamp. > * Typecast the f->m to u32. > > drivers/clk/qcom/clk-rcg2.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c > index e1b1b426fae4..3a78a2a16cf8 100644 > --- a/drivers/clk/qcom/clk-rcg2.c > +++ b/drivers/clk/qcom/clk-rcg2.c > @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, > > static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) > { > - u32 cfg, mask; > + u32 cfg, mask, d_val, not2d_val, n_minus_m; > struct clk_hw *hw = &rcg->clkr.hw; > int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); > > @@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) > if (ret) > return ret; > > + /* Calculate 2d value */ > + d_val = f->n; > + > + n_minus_m = f->n - f->m; > + n_minus_m *= 2; > + > + d_val = clamp(d_val, (u32)f->m, n_minus_m); Use clamp_t(u32, d_val, f->m, n_minus_m) > + not2d_val = ~d_val & mask; > + > ret = regmap_update_bits(rcg->clkr.regmap, > - RCG_D_OFFSET(rcg), mask, ~f->n); > + RCG_D_OFFSET(rcg), mask, not2d_val); > if (ret)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index e1b1b426fae4..3a78a2a16cf8 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { - u32 cfg, mask; + u32 cfg, mask, d_val, not2d_val, n_minus_m; struct clk_hw *hw = &rcg->clkr.hw; int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); @@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) if (ret) return ret; + /* Calculate 2d value */ + d_val = f->n; + + n_minus_m = f->n - f->m; + n_minus_m *= 2; + + d_val = clamp(d_val, (u32)f->m, n_minus_m); + not2d_val = ~d_val & mask; + ret = regmap_update_bits(rcg->clkr.regmap, - RCG_D_OFFSET(rcg), mask, ~f->n); + RCG_D_OFFSET(rcg), mask, not2d_val); if (ret) return ret; }
The display pixel clock has a requirement on certain newer platforms to support M/N as (2/3) and the final D value calculated results in underflow errors. As the current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das <tdas@codeaurora.org> --- [v2] * Update the if else check with clamp. * Typecast the f->m to u32. drivers/clk/qcom/clk-rcg2.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.