Message ID | 20220221181322.5486-2-tdas@codeaurora.org (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | [v2,1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG | expand |
Quoting Taniya Das (2022-02-21 10:13:22) > Support the new numerator and denominator for pixel clock. What SoCs does this patch affect? It would be good to know if it's fixing something wrong with existing SoC support or if it's only for future SoCs that will want to set a 2/3 divide. > > Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") > Signed-off-by: Taniya Das <tdas@codeaurora.org> > Reviewed-by: Stephen Boyd <sboyd@kernel.org>
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 3a78a2a16cf8..cb5610c46882 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -729,6 +729,7 @@ static const struct frac_entry frac_table_pixel[] = { { 2, 9 }, { 4, 9 }, { 1, 1 }, + { 2, 3 }, { } };