diff mbox series

[v3,4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC

Message ID 20220315142915.17764-1-biju.das.jz@bp.renesas.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support | expand

Commit Message

Biju Das March 15, 2022, 2:29 p.m. UTC 
Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v2->v3:
 * Changed the compatible from r9a07g043u-cpg->r9a07g043-cpg
 * Retained the Rb tag from Rob as it is trivial change.
v1->v2:
 * No change
---
 .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml       | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Geert Uytterhoeven March 31, 2022, 9:45 a.m. UTC | #1 
Hi Biju,

On Tue, Mar 15, 2022 at 3:29 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document the device tree binding for the Renesas RZ/G2UL Type-1
> and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
> SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> v2->v3:
>  * Changed the compatible from r9a07g043u-cpg->r9a07g043-cpg
>  * Retained the Rb tag from Rob as it is trivial change.

Thanks for the update!

> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -23,8 +23,9 @@ description: |
>  properties:
>    compatible:
>      enum:
> -      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}
> -      - renesas,r9a07g054-cpg  # RZ/V2L
> +      - renesas,r9a07g043-cpg   # RZ/G2UL{Type-1,Type-2}
> +      - renesas,r9a07g044-cpg   # RZ/G2{L,LC}
> +      - renesas,r9a07g054-cpg   # RZ/V2L

No need to increase the number of spaces before the hashmark.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19, with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..b728a677222e 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -10,7 +10,7 @@  maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
 description: |
-  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
+  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
   Standby Mode share the same register block.
 
   They provide the following functionalities:
@@ -23,8 +23,9 @@  description: |
 properties:
   compatible:
     enum:
-      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}
-      - renesas,r9a07g054-cpg  # RZ/V2L
+      - renesas,r9a07g043-cpg   # RZ/G2UL{Type-1,Type-2}
+      - renesas,r9a07g044-cpg   # RZ/G2{L,LC}
+      - renesas,r9a07g054-cpg   # RZ/V2L
 
   reg:
     maxItems: 1