From patchwork Mon Apr 18 13:21:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A056C38A2C for ; Mon, 18 Apr 2022 14:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245684AbiDRO3S (ORCPT ); Mon, 18 Apr 2022 10:29:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245685AbiDRO1b (ORCPT ); Mon, 18 Apr 2022 10:27:31 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF28252E77; Mon, 18 Apr 2022 06:22:31 -0700 (PDT) X-UUID: a973e584414c4509b95678c1e3048e21-20220418 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:41f795b1-590a-4880-92c7-91b605d39997,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:41f795b1-590a-4880-92c7-91b605d39997,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:54c817f0-da02-41b4-b6df-58f4ccd36682,C OID:28c04104b64a,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: a973e584414c4509b95678c1e3048e21-20220418 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 433432596; Mon, 18 Apr 2022 21:22:25 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Apr 2022 21:22:23 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 4/7] clk: mediatek: reset: Add reset.h Date: Mon, 18 Apr 2022 21:21:51 +0800 Message-ID: <20220418132154.7401-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a new file "reset.h" to place some definitions for clock reset. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mtk.h | 10 +--------- drivers/clk/mediatek/reset.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 9 deletions(-) create mode 100644 drivers/clk/mediatek/reset.h diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index dafdf30fe94e..dfb0549ceb6c 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -12,6 +12,7 @@ #include #include #include +#include #define MAX_MUX_GATE_BIT 31 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) @@ -178,12 +179,6 @@ struct mtk_clk_divider { .div_width = _width, \ } -enum mtk_reset_version { - MTK_RST_V1 = 0, - MTK_RST_V2, - MTK_RST_MAX, -}; - int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); @@ -196,9 +191,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -int mtk_clk_register_rst_ctrl(struct device_node *np, - u32 reg_num, u16 reg_ofs, u8 version); - struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h new file mode 100644 index 000000000000..0af77531b918 --- /dev/null +++ b/drivers/clk/mediatek/reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __DRV_CLK_MTK_RESET_H +#define __DRV_CLK_MTK_RESET_H + +#include + +enum mtk_reset_version { + MTK_RST_V1 = 0, + MTK_RST_V2, + MTK_RST_MAX, +}; + +int mtk_clk_register_rst_ctrl(struct device_node *np, + u32 reg_num, u16 reg_ofs, u8 version); + +#endif /* __DRV_CLK_MTK_RESET_H */