diff mbox series

[V2,09/12] clk: mediatek: reset: Add support for input offset and bit from DT

Message ID 20220420130527.23200-10-rex-bc.chen@mediatek.com (mailing list archive)
State Changes Requested, archived
Headers show
Series Cleanup MediaTek clk reset drivers and support MT8192/MT8195 | expand

Commit Message

Rex-BC Chen (陳柏辰) April 20, 2022, 1:05 p.m. UTC 
To use the clock reset function easier, we implement the of_xlate.
This function is only adopted in version MTK_SET_CLR because of
the method of id calculation.

There is no impact for original use. If the argument number is not
larger than 1, it will return original id.

With this implementation if we want to set offset 0x120 and bit 16,
we can just write something like "resets = <&infra_rst 0x120 16>;".

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 24 ++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h |  1 +
 2 files changed, 25 insertions(+)

Comments

Rex-BC Chen (陳柏辰) April 21, 2022, 5:36 a.m. UTC | #1 
On Wed, 2022-04-20 at 21:05 +0800, Rex-BC Chen wrote:
> To use the clock reset function easier, we implement the of_xlate.
> This function is only adopted in version MTK_SET_CLR because of
> the method of id calculation.
> 
> There is no impact for original use. If the argument number is not
> larger than 1, it will return original id.
> 
> With this implementation if we want to set offset 0x120 and bit 16,
> we can just write something like "resets = <&infra_rst 0x120 16>;".
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>  drivers/clk/mediatek/reset.c | 24 ++++++++++++++++++++++++
>  drivers/clk/mediatek/reset.h |  1 +
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/reset.c
> b/drivers/clk/mediatek/reset.c
> index 1173111af3ab..dbe812062bf5 100644
> --- a/drivers/clk/mediatek/reset.c
> +++ b/drivers/clk/mediatek/reset.c
> @@ -59,6 +59,20 @@ static const struct reset_control_ops
> mtk_reset_ops_set_clr = {
>  	.reset = mtk_reset_set_clr,
>  };
>  
> +static int reset_xlate(struct reset_controller_dev *rcdev,
> +		       const struct of_phandle_args *reset_spec)
> +{
> +	unsigned int offset, bit;
> +
> +	if (reset_spec->args_count <= 1)
> +		return reset_spec->args[0];
> +
> +	offset = reset_spec->args[0];
> +	bit = reset_spec->args[1];
> +
> +	return (offset >> 4) * 32 + bit;
> +}
> +
>  static const struct reset_control_ops *rst_op[MTK_RST_MAX] = {
>  	[MTK_RST_SIMPLE] = &reset_simple_ops,
>  	[MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr,
> @@ -98,6 +112,11 @@ int mtk_clk_register_rst_ctrl(struct device_node
> *np,
>  	data->rcdev.ops = rst_op[desc->version];
>  	data->rcdev.of_node = np;
>  
> +	if (desc->version == MTK_RST_SET_CLR) {
> +		data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 
> 1);
> +		data->rcdev.of_xlate = reset_xlate;
> +	}
> +
>  	ret = reset_controller_register(&data->rcdev);
>  	if (ret) {
>  		pr_err("could not register reset controller: %d\n",
> ret);
> @@ -143,6 +162,11 @@ int mtk_clk_register_rst_ctrl_with_dev(struct
> device *dev,
>  	data->rcdev.of_node = np;
>  	data->rcdev.dev = dev;
>  
> +	if (desc->version == MTK_RST_SET_CLR) {
> +		data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 
> 1);
> +		data->rcdev.of_xlate = reset_xlate;
> +	}
> +
>  	ret = devm_reset_controller_register(dev, &data->rcdev);
>  	if (ret)
>  		dev_err(dev, "could not register reset controller:
> %d\n", ret);
> diff --git a/drivers/clk/mediatek/reset.h
> b/drivers/clk/mediatek/reset.h
> index 30559bf45f7e..4cfc281fc50d 100644
> --- a/drivers/clk/mediatek/reset.h
> +++ b/drivers/clk/mediatek/reset.h
> @@ -19,6 +19,7 @@ struct mtk_clk_rst_desc {
>  	u8 version;
>  	u32 reg_num;
>  	u16 reg_ofs;
> +	int reset_n_cells;
>  };
>  
>  struct mtk_clk_rst_data {

Hello all,

I think reset_xlate can also support for MTK_RST_SIMPLE.
If this patch is acceptable, I will modify for MTK_RST_SIMPLE in next
version.

BRs,
Rex
AngeloGioacchino Del Regno April 21, 2022, 9:07 a.m. UTC | #2 
Il 20/04/22 15:05, Rex-BC Chen ha scritto:
> To use the clock reset function easier, we implement the of_xlate.
> This function is only adopted in version MTK_SET_CLR because of
> the method of id calculation.
> 
> There is no impact for original use. If the argument number is not
> larger than 1, it will return original id.
> 
> With this implementation if we want to set offset 0x120 and bit 16,
> we can just write something like "resets = <&infra_rst 0x120 16>;".
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>   drivers/clk/mediatek/reset.c | 24 ++++++++++++++++++++++++
>   drivers/clk/mediatek/reset.h |  1 +
>   2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
> index 1173111af3ab..dbe812062bf5 100644
> --- a/drivers/clk/mediatek/reset.c
> +++ b/drivers/clk/mediatek/reset.c
> @@ -59,6 +59,20 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
>   	.reset = mtk_reset_set_clr,
>   };
>   
> +static int reset_xlate(struct reset_controller_dev *rcdev,
> +		       const struct of_phandle_args *reset_spec)
> +{
> +	unsigned int offset, bit;
> +
> +	if (reset_spec->args_count <= 1)
> +		return reset_spec->args[0];
> +
> +	offset = reset_spec->args[0];
> +	bit = reset_spec->args[1];
> +
> +	return (offset >> 4) * 32 + bit;
> +}
> +
>   static const struct reset_control_ops *rst_op[MTK_RST_MAX] = {
>   	[MTK_RST_SIMPLE] = &reset_simple_ops,
>   	[MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr,
> @@ -98,6 +112,11 @@ int mtk_clk_register_rst_ctrl(struct device_node *np,
>   	data->rcdev.ops = rst_op[desc->version];
>   	data->rcdev.of_node = np;
>   
> +	if (desc->version == MTK_RST_SET_CLR) {

...following my previous advice to use switch(version), this would fit in
just fine :-)

Everything else looks ok.

Cheers,
Angelo
Rex-BC Chen (陳柏辰) April 22, 2022, 5:06 a.m. UTC | #3 
On Thu, 2022-04-21 at 11:07 +0200, AngeloGioacchino Del Regno wrote:
> Il 20/04/22 15:05, Rex-BC Chen ha scritto:
> > To use the clock reset function easier, we implement the of_xlate.
> > This function is only adopted in version MTK_SET_CLR because of
> > the method of id calculation.
> > 
> > There is no impact for original use. If the argument number is not
> > larger than 1, it will return original id.
> > 
> > With this implementation if we want to set offset 0x120 and bit 16,
> > we can just write something like "resets = <&infra_rst 0x120 16>;".
> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >   drivers/clk/mediatek/reset.c | 24 ++++++++++++++++++++++++
> >   drivers/clk/mediatek/reset.h |  1 +
> >   2 files changed, 25 insertions(+)
> > 
> > diff --git a/drivers/clk/mediatek/reset.c
> > b/drivers/clk/mediatek/reset.c
> > index 1173111af3ab..dbe812062bf5 100644
> > --- a/drivers/clk/mediatek/reset.c
> > +++ b/drivers/clk/mediatek/reset.c
> > @@ -59,6 +59,20 @@ static const struct reset_control_ops
> > mtk_reset_ops_set_clr = {
> >   	.reset = mtk_reset_set_clr,
> >   };
> >   
> > +static int reset_xlate(struct reset_controller_dev *rcdev,
> > +		       const struct of_phandle_args *reset_spec)
> > +{
> > +	unsigned int offset, bit;
> > +
> > +	if (reset_spec->args_count <= 1)
> > +		return reset_spec->args[0];
> > +
> > +	offset = reset_spec->args[0];
> > +	bit = reset_spec->args[1];
> > +
> > +	return (offset >> 4) * 32 + bit;
> > +}
> > +
> >   static const struct reset_control_ops *rst_op[MTK_RST_MAX] = {
> >   	[MTK_RST_SIMPLE] = &reset_simple_ops,
> >   	[MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr,
> > @@ -98,6 +112,11 @@ int mtk_clk_register_rst_ctrl(struct
> > device_node *np,
> >   	data->rcdev.ops = rst_op[desc->version];
> >   	data->rcdev.of_node = np;
> >   
> > +	if (desc->version == MTK_RST_SET_CLR) {
> 
> ...following my previous advice to use switch(version), this would
> fit in
> just fine :-)
> 
> Everything else looks ok.
> 
> Cheers,
> Angelo

Hello Angelo,

I will add this judgement in reset_xlate()

BRs,
Rex
diff mbox series

Patch

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index 1173111af3ab..dbe812062bf5 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -59,6 +59,20 @@  static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
+static int reset_xlate(struct reset_controller_dev *rcdev,
+		       const struct of_phandle_args *reset_spec)
+{
+	unsigned int offset, bit;
+
+	if (reset_spec->args_count <= 1)
+		return reset_spec->args[0];
+
+	offset = reset_spec->args[0];
+	bit = reset_spec->args[1];
+
+	return (offset >> 4) * 32 + bit;
+}
+
 static const struct reset_control_ops *rst_op[MTK_RST_MAX] = {
 	[MTK_RST_SIMPLE] = &reset_simple_ops,
 	[MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr,
@@ -98,6 +112,11 @@  int mtk_clk_register_rst_ctrl(struct device_node *np,
 	data->rcdev.ops = rst_op[desc->version];
 	data->rcdev.of_node = np;
 
+	if (desc->version == MTK_RST_SET_CLR) {
+		data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+		data->rcdev.of_xlate = reset_xlate;
+	}
+
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
 		pr_err("could not register reset controller: %d\n", ret);
@@ -143,6 +162,11 @@  int mtk_clk_register_rst_ctrl_with_dev(struct device *dev,
 	data->rcdev.of_node = np;
 	data->rcdev.dev = dev;
 
+	if (desc->version == MTK_RST_SET_CLR) {
+		data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+		data->rcdev.of_xlate = reset_xlate;
+	}
+
 	ret = devm_reset_controller_register(dev, &data->rcdev);
 	if (ret)
 		dev_err(dev, "could not register reset controller: %d\n", ret);
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 30559bf45f7e..4cfc281fc50d 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -19,6 +19,7 @@  struct mtk_clk_rst_desc {
 	u8 version;
 	u32 reg_num;
 	u16 reg_ofs;
+	int reset_n_cells;
 };
 
 struct mtk_clk_rst_data {