From patchwork Wed Apr 20 13:05:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7611C433F5 for ; Wed, 20 Apr 2022 13:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378782AbiDTNI0 (ORCPT ); Wed, 20 Apr 2022 09:08:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378773AbiDTNIY (ORCPT ); Wed, 20 Apr 2022 09:08:24 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28AD8222AC; Wed, 20 Apr 2022 06:05:37 -0700 (PDT) X-UUID: 4a7794cfb1334ff78f2ef6ee569b40a5-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:82528a0a-2cf6-477e-a1bb-8f6a0b76cbe3,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:1ee65cf0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 4a7794cfb1334ff78f2ef6ee569b40a5-20220420 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1192217164; Wed, 20 Apr 2022 21:05:32 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:30 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 11/12] clk: mediatek: reset: Add infra_ao reset support for MT8192 Date: Wed, 20 Apr 2022 21:05:26 +0800 Message-ID: <20220420130527.23200-12-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The infra_ao reset is needed for MT8192. Therefore, we add this patch to support it. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 11 +++++++++++ include/dt-bindings/reset/mt8192-resets.h | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index ab27cd66b866..7926b83b9035 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1114,6 +1114,13 @@ static const struct mtk_gate top_clks[] = { GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SET_CLR, + .reg_num = 4, + .reg_ofs = 0x0, + .reset_n_cells = 2, +}; + #define MT8192_PLL_FMAX (3800UL * MHZ) #define MT8192_PLL_FMIN (1500UL * MHZ) #define MT8192_INTEGER_BITS 8 @@ -1239,6 +1246,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) if (r) goto free_clk_data; + r = mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); + if (r) + goto free_clk_data; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) goto free_clk_data; diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index be9a7ca245b9..feac1ac85906 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 +/* TOPRGU */ #define MT8192_TOPRGU_MM_SW_RST 1 #define MT8192_TOPRGU_MFG_SW_RST 2 #define MT8192_TOPRGU_VENC_SW_RST 3 @@ -27,4 +28,14 @@ #define MT8192_TOPRGU_SW_RST_NUM 23 +/* INFRA RST0 */ +#define MT8192_INFRA_RST0_LVTS_AP_RST 0 +/* INFRA RST2 */ +#define MT8192_INFRA_RST2_PCIE_PHY_RST 15 +/* INFRA RST3 */ +#define MT8192_INFRA_RST3_PTP_RST 5 +/* INFRA RST4 */ +#define MT8192_INFRA_RST4_LVTS_MCU 12 +#define MT8192_INFRA_RST4_PCIE_TOP 1 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */